Inventor

GUHA JAYDIP

US24 patents

⚠️ This page may combine multiple inventors who share the name “GUHA JAYDIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUHA JAYDIP

MICRON TECHNOLOGY INC

Conductive structures, wordlines and transistors

Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith

Memory cells, arrays of memory cells, and methods of forming memory cells

Array of vertical transistors and method used in forming an array of vertical transistors

Methods of forming memory arrays and semiconductor constructions

Array of vertical transistors and method used in forming an array of vertical transistors

Integrated assemblies and methods of forming integrated assemblies

Integrated assemblies and methods of forming integrated assemblies

Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions

Methods of forming semiconductor constructions

Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells

Apparatus with doped surfaces, and related methods with in situ doping

Memory device including calibration operation and transistor having adjustable threshold voltage

Conductive structures, wordlines and transistors

Methods of forming a vertical transistor

Recessed access devices and methods of forming a recessed access devices

GUHA JAYDIP

Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith

Methods of forming memory arrays and semiconductor constructions

HEINECK LARS P

Integrated circuit arrays and semiconductor constructions

MATHEW SURAJ

Gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices

HEINECK LARS

Memory cells, arrays of memory cells, and methods of forming memory cells

KARDA KAMAL M

Memory cells having capacitor dielectric directly against a transistor source/drain region

NANYA TECHNOLOGY CORP

Method of manufacturing sidewall spacers on a memory device

DURGA PANDA

Method of manufacturing sidewall spacers on a memory device