Inventor

DYER THOMAS W

US84 patents

⚠️ This page may combine multiple inventors who share the name “DYER THOMAS W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DYER THOMAS W

IBM

Device structures including backside contacts, and methods for forming same

Method of manufacturing a body-contacted finfet

Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure

Deep trench (DT) metal-insulator-metal (MIM) capacitor

Structure and methods for stress concentrating spacer

Two-sided semiconductor-on-insulator structures and methods of manufacturing the same

Deep trench capacitor with buried plate electrode and isolation collar

Method for forming self-aligned, dual silicon nitride liner for CMOS devices

Self-aligned dual segment liner and method of manufacturing the same

Vertical gate top engineering for improved GC and CB process windows

Selective local metal cap layer formation for improved electromigration behavior

Silicon-on-insulator substrate with built-in substrate junction

Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure

Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor

SOI substrates and SOI devices, and methods for forming the same

Structure and method to form improved isolation in a semiconductor device

CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy

High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching

High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching

CMOS gate conductor having cross-diffusion barrier

Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure

Process for making FinFET device with body contact and buried oxide junction isolation

TTO nitride liner for improved collar protection and TTO reliability

High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching

Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolation

High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same

Embedded interconnects, and methods for forming same

Forming conductive stud for semiconductive devices

Strained MOSFETs on separated silicon layers

Vertical gate conductor with buried contact layer for increased contact landing area

CMOS devices with hybrid channel orientations and method for fabricating the same

CMOS devices with hybrid channel orientations and method for fabricating the same

Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation

Selective local metal cap layer formation for improved electromigration behavior

Measuring metal line spacing in semiconductor devices

Selective local metal cap layer formation for improved electromigration behavior

Complementary field effect transistors having embedded silicon source and drain regions

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Embedded interconnects, and methods for forming same

DYER THOMAS W

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Method of forming a planar field effect transistor structure with recesses for epitaxially deposited source/drain regions

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

INFINEON TECHNOLOGIES CORP

Method for forming TTO nitride liner for improved collar protection and TTO reliability

Vertical semiconductor devices

SAMSUNG ELECTRONICS CO LTD

Methods for forming self-aligned dual stress liners for CMOS semiconductor devices

YANG JONG HO

Methods of forming p-channel field effect transistors having SiGe source/drain regions

INFINEON TECHNOLOGIES AG

Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts

CHEN XIANGDONG

CMOS devices with stressed channel regions, and methods for fabricating the same

HAN JIN-PING

Semiconductor devices and methods of manufacture thereof