Inventor

EITAN BENNY

IL100 patents

⚠️ This page may combine multiple inventors who share the name “EITAN BENNY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EITAN BENNY

INTEL CORP

Processor executing unpack instruction to interleave data elements from two packed data

Method for performing multiply-add operations on packed data

Method for unpacking a plurality of packed data into a result packed data

Microprocessor capable of unpacking packed data

Method and apparatus for performing multiply-subtract operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Method of sorting numbers to obtain maxima/minima values with ordering

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

Method for packing a plurality of packed data elements in response to a pack instruction

Processor performing packed data multiplication

Method for performing shift operations on packed data

Microprocessor capable of unpacking packed data in response to a unpack instruction

Apparatus for performing multiply-add operations on packed data

Apparatus for performing multiply-add operations on packed data

Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file

Method and apparatus for performing multiply and accumulate operations on packed data

Apparatus for performing packed shift operations

Apparatus for performing packed shift operations

Method for executing instructions that operate on different data types stored in the same single logical register file

System for signal processing using multiply-add operations

Emptying packed data state during execution of packed data instructions

Computer implemented method for transferring packed data between register files and memory

Processor for performing shift operations on packed data

Method for performing an inverse cosine transfer function for use with multimedia information

Executing different instructions that cause different data type operations to be performed on single logical register file

Method for multiplying packed data

Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits

Computer system performing a two-dimensional rotation of packed data representing multimedia information

Processor for performing multiply-add operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Processor with instructions that operate on different data types stored in the same single logical register file

Emptying packed data state during execution of packed data instructions

Method of sorting numbers to obtain maxima/minima values with ordering

Method for performing population counts on packed data types

Method of sorting signed numbers and solving absolute differences using packed instructions

Method for performing multiply-substrate operations on packed data

Microarchitecture for implementing an instruction to clear the tags of a stack reference register file

Computer system performing an inverse cosine transfer function for use with multimedia information

Processor with instructions that operate on different data types stored in the same single logical register file

Multiply add functional unit capable of executing SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE and CLASS instructions

Methods and apparatus for determination of packet sizes when transferring packets via a network

Method and apparatus for performing packed shift operations

SPERBER ZEEV

Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits

Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits

PELEG ALEXANDER

Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register

Processor for performing multiply-add operations on packed data

GINZBURG BORIS

Multiplying and adding matrices

PINEIRO JOSE-ALEJANDRO

Math circuit for estimating a transcendental function

ORENSTIEN DORON

Mixing instructions with different register sizes

PELEG ALEXANDER D

Processor for performing multiply-add operations on packed data