Inventor

CHANG PETER L D

US45 patents

⚠️ This page may combine multiple inventors who share the name “CHANG PETER L D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG PETER L D

INTEL CORP

Self-aligned contacts for transistors

Independently accessed double-gate and tri-gate transistors in same process flow

Integration of planar and tri-gate devices on the same substrate

Independently controlled, double gate nanowire memory cell with self-aligned contacts

Expitaxial fabrication of fins for FinFET devices

Integration of a floating body memory on SOI with logic transistors on bulk substrate

Method of preparing active silicon regions for CMOS or other devices

Memory with split gate devices and method of fabrication

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Epitaxial fabrication of fins for FinFET devices

Independently accessed double-gate and tri-gate transistors in same process flow

Isolating semiconductor device structures

Methods for forming semiconductor wires and resulting devices

Memory cell using silicon carbide

Integration of a floating body memory on SOI with logic transistors on bulk substrate

Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate

Electro-optical assembly including a glass bridge

Low cost integration of optical components in planar lightwave circuits

Independently controlled, double gate nanowire memory cell with self-aligned contacts

Method and resultant structure for floating body memory on bulk wafer

Method and resultant structure for floating body memory on bulk wafer

Independently accessed double-gate and tri-gate transistors in same process flow

Memory with split gate devices and method of fabrication

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate

Floating body memory array

Methods for forming semiconductor wires and resulting devices

CHANG PETER L D

Floating body memory cell having gates favoring different conductivity type regions

Integration of planar and tri-gate devices on the same substrate

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Independently accessed double-gate and tri-gate transistors

Independently accessed double-gate and tri-gate transistors in same process flow

LOCKHEED SANDERS INC

Dual mode energy detector having monolithic integrated circuit construction

Photoconductive semiconductor control device

APPLE INC

Silicon photonics using off-cut wafer having top-side vertical outcoupler from etched cavity