Inventor

VENKUMAHANTI SURESH K

US22 patents

⚠️ This page may combine multiple inventors who share the name “VENKUMAHANTI SURESH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENKUMAHANTI SURESH K

QUALCOMM INC

Speculative addressing using a virtual address-to-physical address page crossing buffer

Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process

Shared interrupt controller for a multi-threaded processor

System and method of selectively accessing a register file

Data cache way prediction

Instruction cache having a multi-bit way prediction mask

Using the least significant bits of a called function&#39;s address to switch processor modes

System and method to select a packet format based on a number of executed threads

Overlap checking for a translation lookaside buffer (TLB)

VENKUMAHANTI SURESH K

System and method to access a portion of a level two memory and a level one memory

Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor

Low latency two-level interrupt controller interface to multi-threaded processor

Bimodal branch predictor encoded in a branch instruction

Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold

Interleaved architecture tracing and microarchitecture tracing

Associating data for events occurring in software threads with synchronized clock cycle counters

SASSONE PETER G

Hybrid write-through/write-back cache policy managers, and related systems and methods

PLONDKE ERICH JAMES

Table call instruction for frequently called functions

INGLE AJAY ANANT

System and method of executing instructions in a multi-stage data processing pipeline

PLONDKE ERICH J

Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination

KOOB CHRISTOPHER EDWARD

Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors

CODRESCU LUCIAN

System and method of processing hierarchical very long instruction packets

Using the least significant bits of a called function's address to switch processor modes