Inventor

ANANTHAKRISHNAN AVINASH N

US69 patents

⚠️ This page may combine multiple inventors who share the name “ANANTHAKRISHNAN AVINASH N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANANTHAKRISHNAN AVINASH N

INTEL CORP

Dynamically allocating a power budget over multiple domains of a processor

Enabling a non-core domain to control memory bandwidth in a processor

Multi-level loops for computer processor control

Dynamically controlling cache size to maximize energy efficiency

Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain

Dynamically controlling cache size to maximize energy efficiency

Techniques to enable communication between a processor and voltage regulator

Performing cross-domain thermal control in a processor

Multi-level loops for computer processor control

Multi-level loops for computer processor control

User level control of power management policies

Enabling a non-core domain to control memory bandwidth in a processor

Controlling a turbo mode frequency of a processor

Enabling a non-core domain to control memory bandwidth in a processor

Controlling temperature of multiple domains of a multi-domain processor using a cross-domain margin

Enhanced power management for support of priority system events

Techniques to enable communication between a processor and voltage regulator

Thread scheduling using processing engine information

Enhanced power management for support of priority system events

Enhanced power management for support of priority system events

Controlling a performance state of a processor using a combination of package and thread hint information

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

Processor voltage control using running average value

Constraining processor operation based on power envelope information

Controlling a turbo mode frequency of a processor

Controlling operating frequency of a core domain based on operating condition of a non-core domain of a multi-domain processor

Dynamically allocating a power budget over multiple domains of a processor

Multi-level loops for computer processor control

Enhanced power management for support of priority system events

System, apparatus and method for providing hardware feedback information in a processor

User level control of power management policies

User level control of power management policies

Techniques to enable communication between a processor and voltage regulator

Techniques to enable communication between a processor and voltage regulator

Techniques to enable communication between a processor and voltage regulator

System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor

ANANTHAKRISHNAN AVINASH N

Dynamically controlling cache size to maximize energy efficiency

Dynamically allocating a power budget over multiple domains of a processor

Controlling a turbo mode frequency of a processor

Enabling a non-core domain to control memory bandwidth in a processor

Estimating temperature of a processor core in a low power state without thermal sensor information

Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor

SISTLA KRISHNAKANTH V

User level control of power management policies

Dynamically modifying a power/performance tradeoff based on processor utilization

Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains

VARMA ANKUSH

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

Microprocessor-assisted auto-calibration of voltage regulators

ROTEM EFRAIM

Apparatus and method for high current protection

MOSES JAIDEEP

Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing

WEISSMANN ELIEZER

Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation