Inventor

CAULFIELD IAN MICHAEL

GB31 patents

⚠️ This page may combine multiple inventors who share the name “CAULFIELD IAN MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAULFIELD IAN MICHAEL

ADVANCED RISC MACH LTD

Apparatus and method for controlling allocation of data into a cache storage

Fusion of instructions by delaying handling of a partial subset of a fusible group of instructions

Apparatus and method for controlling allocation of instructions into an instruction cache storage

Cache access detection and prediction

Apparatus and method for suspending execution of a thread in response to a hint instruction

Speculative side-channel hint instruction

Controlling use of data determined by a resolve-pending speculative operation

Encoding of input to storage circuitry

Mode switching in dependence upon a number of active threads

Apparatus and method for sharing branch information storage entries between threads that share an address translation regime

Method and apparatus for interrupt handling

Arbitration of requests requiring a variable number of resources

Apparatus and method for predicting source operand values and optimized processing of instructions

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

Tracking speculative data caching

Apparatus and method for prefetching data items

Register-based matrix multiplication with multiple matrices per register

Cache control in presence of speculative read operations

Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method

Control of bulk memory instructions

Apparatus and method for supporting out-of-order program execution of instructions

Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instruction

Execution of micro-operations

Ranking items

Apparatus and method for estimating a shift amount when performing floating-point subtraction

Determining a predicted behaviour for processing of instructions

Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry

Processor and method for processing instructions using at least one processing pipeline

Handling stalling event for multiple thread pipeline, and triggering action based on information access delay

Data storage

PENTON ANTONY JOHN

Apparatus and method for performing fused multiply add floating point operation