Inventor

PENTON ANTONY JOHN

GB39 patents

⚠️ This page may combine multiple inventors who share the name “PENTON ANTONY JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENTON ANTONY JOHN

ADVANCED RISC MACH LTD

Auxiliary circuit structure in a split-lock dual processor system

Performance by reducing transaction request ordering requirements

Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits

Apparatus and method for suspending execution of a thread in response to a hint instruction

Apparatus and method for checking output data during redundant execution of instructions

Improving the responsiveness of an apparatus to certain interrupts

Handling access attributes for data accesses

Programmable instruction buffering for accumulating a burst of instructions

Mode switching in dependence upon a number of active threads

Dynamic cache allocation policy adaptation in a data processing apparatus

Synchronisation of signals between asynchronous logic

Check data encoding using parallel lane encoders

Error correction code

Instruction issue according to in-order or out-of-order execution modes

Asymmetric coherency protocol for first and second processing circuitry having different levels of fault protection or fault detection

Selectively suppressing time intensive instructions based on a control value

Handling access attributes for data accesses

Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

Apparatus and branch prediction circuitry having first and second branch prediction schemes, and method

Cache prefetching

Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory address

Apparatus and method for increasing resilience to faults

System register access

Apparatus and method for detecting errors in a memory device

Allocating a register to an instruction using register index information

Determining a predicted behaviour for processing of instructions

Apparatus and method for increasing resilience to faults

Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitry

Instruction prefetch halting upon predecoding predetermined instruction types

Processor exception handling using a branch target cache

PENTON ANTONY JOHN

Apparatus and method for error correction of data values in a storage device

Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations

Register state saving and restoring

Handling of hard errors in a cache of a data processing apparatus

Apparatus and method for performing fused multiply add floating point operation

CRASKE SIMON JOHN

Error correction in a set associative storage device

Area and power efficient data coherency maintenance

VASEKIN VLADIMIR

Thread selection for multithreaded processing

PATHIRANE CHILODA ASHAN SENERATH

Debugging a multiprocessor system that switches between a locked mode and a split mode