Inventor

DE KAUSHIK

US17 patents

⚠️ This page may combine multiple inventors who share the name “DE KAUSHIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DE KAUSHIK

SYNOPSYS INC

Method and apparatus for extracting assume properties from a constrained random test-bench

Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference

Machine learning (ML)-based static verification for derived hardware-design elements

Minimizing crossover paths for functional verification of a circuit description

Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements

Ranking verification results for root cause analysis

State table complexity reduction in a hierarchical verification flow

Low-power static signoff verification from within an implementation tool

Accurate glitch detection

Voltage reconciliation in multi-level power managed systems

Verification of circuit structures including sub-structure variants

LSI LOGIC CORP

System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code

Defect isolation using scan-path testing and electron beam probing in multi-level high density asics

Protecting proprietary asic design information using boundary scan on selective inputs and outputs

Test shells for protecting proprietary information in asic cores

IDDQ test solution for large asics

DE KAUSHIK

Technique for honoring multi-cycle path semantics in RTL simulation