Inventor

NARAYANAN PRAKASH

IN41 patents

⚠️ This page may combine multiple inventors who share the name “NARAYANAN PRAKASH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARAYANAN PRAKASH

TEXAS INSTRUMENTS INC

Scan chain masking qualification circuit shift register and bit-field decoders

Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry

Compressed scan chains with three input mask gates and registers

Compressed scan chains with three input mask gates and registers

On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems

Decompressed scan chain masking circuit shift register with log2(n/n) cells

Scan chain self-testing of lockstep cores on reset

Delay fault testing of pseudo static controls

Full pad coverage boundary scan

Multiple input signature register analysis for digital circuitry

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Dynamic generation of ATPG mode signals for testing multipath memory circuit

Phase controlled codec block scan of a partitioned circuit device

False path timing exception handler circuit

False path timing exception handler circuit

Scan chain self-testing of lockstep cores on reset

Transistion fault testing of funtionally asynchronous paths in an integrated circuit

Full pad coverage boundary scan

Multiple input signature register analysis for digital circuitry

Path based controls for ATE mode testing of multicell memory circuit

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Dynamic generation of ATPG mode signals for testing multipath memory circuit

Phase controlled codec block scan of a partitioned circuit device

False path timing exception handler circuit

Path based controls for ATE mode testing of multicell memory circuit

Scan chain self-testing of lockstep cores on reset

Full pad coverage boundary scan

Delay fault testing of pseudo static controls

Transition fault testing of functionally asynchronous paths in an integrated circuit

Delay fault testing of pseudo static controls

Circuits and methods for dynamic allocation of scan test resources

Testing read-only memory using memory built-in self-test controller

Testing read-only memory using memory built-in self-test controller

Area efficient parallel test data path for embedded memories

Full pad coverage boundary scan

Area efficient parallel test data path for embedded memories

NARAYANAN PRAKASH

Masking circuit removing unknown bit from cell in scan chain

On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems

MITTAL RAJESH

Integrated circuits capable of generating test mode control signals for scan tests

PODDUTUR SUMANTH REDDY

IC delaying flip-flop output partial clock cycle for equalizing current

MICROSOFT TECHNOLOGY LICENSING LLC

Secure cross-tenant access