Inventor

FUJIWARA YOSHINORI

US52 patents

⚠️ This page may combine multiple inventors who share the name “FUJIWARA YOSHINORI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FUJIWARA YOSHINORI

MICRON TECHNOLOGY INC

Apparatuses and methods for flexible fuse transmission

Apparatuses and methods for flexible fuse transmission

Apparatuses and methods for flexible fuse transmission

Redundant memory array for replacing memory sections of main memory

JTAG controlled self-repair after packaging

Systems and methods for defect testing of externally accessible integrated circuit interconnects

JTAG controlled self-repair after packaging

Selectable memory word line deactivation

Apparatuses, systems, and methods for error correction

Transmit line monitoring circuitry, and related methods, devices, and systems

Systems and methods for power savings in row repaired memory

Systems and methods for power savings in row repaired memory

Redundant memory array for replacing memory sections of main memory

Systems and methods for defect testing of externally accessible integrated circuit interconnects

Row addressing

Apparatuses and methods including dice latches in a semiconductor device

Asynchronous signal to command timing calibration for testing accuracy

Memory built-in self-test with adjustable pause time

Apparatuses and methods including dice latches in a semiconductor device

Microelectronic device testing, and related devices, systems, and methods

Interconnected command/address resources

Apparatuses, systems, and methods for error correction

Systems and methods for testing redundant fuse latches in a memory device

Memory device random option inversion

Apparatus with adjustable diagnostic mechanism and methods for operating the same

Test mode security circuit

Memory read masking

Methods and apparatuses to detect test probe contact at external terminals

Apparatuses and methods for forcing memory cell failures in a memory device

Apparatuses and methods for self-test mode abort circuit

Identifying high impedance faults in a memory device

Apparatuses and methods for multi-memory array accesses

Selectable memory word line deactivation

Apparatuses and methods for fuse error detection

Apparatuses and methods for refresh address masking

Repair element availability communication

Apparatuses and methods for bad row mode

Self-repair verification

FUJIWARA YOSHINORI

JTAG controlled self-repair after packaging

Redundant memory array for replacing memory sections of main memory

Redundant memory array for replacing memory sections of main memory

JTAG controlled self-repair after packaging

Methods for defect testing of externally accessible integrated circuit interconnects

MITSUBISHI ELECTRIC CORP

Semiconductor memory device having redundancy structure with defect relieving function

Devices for storing and accumulating defect information, semiconductor device and device for testing the same

RENESAS TECH CORP

Semiconductor device with process monitor circuit and test method thereof

FUJI TOOL CO LTD

Gage for use in welding

BANDO CHEMICAL IND

Method and apparatus for making a blade for electrophotographic devices

NAKANISHI TAKUYA

Row addressing

USHIO ELECTRIC INC

Workpiece stage of a resist curing device