Inventor

ROYER JR ROBERT J

US43 patents

⚠️ This page may combine multiple inventors who share the name “ROYER JR ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROYER JR ROBERT J

INTEL CORP

Interface for a block addressable mass storage system

Disk block allocation optimization methodology with accommodation for file system cluster size greater than operating system memory page size

Method and apparatus for efficient command queuing within a serial ATA environment

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Repurposing NAND ready/busy pin as completion interrupt

Method and system to cache metadata

In-system provisioning of firmware for a hardware platform

Delta checkpoints for a non-volatile memory indirection table

Maintaining cache integrity by recording write addresses in a log

Dynamic master/slave configuration for multiple expansion modules

Method and apparatus to generate cache data

Method and apparatus for generating a transportable physical level data block trace

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

NVDIMM emulation using a host memory buffer

In-system provisioning of firmware for a hardware platform

Dynamically changing between latency-focused read operation and bandwidth-focused read operation

Cache write integrity logging

Dynamic master/slave configuration for multiple expansion modules

Optimally mapping a memory device

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Fast page fault handling process implemented on persistent memory

Fast self-refresh exit power state

Memory latency management

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Memory latency management

Memory management

Maintaining disk cache coherency in multiple operating system environment

Transportation of main memory and intermediate memory contents

Dynamic adaptive clocking for non-common-clock interfaces

Architectures and techniques for providing low-power storage mechanisms

Dynamic adaptive clocking for non-common-clock interfaces

Non-volatile memory interface

Non-volatile memory interface

I/O layout footprint for multiple 1LM/2LM configurations

Techniques to reduce memory power consumption during a system idle state

Technologies for protecting data in an asymmetric storage volume

ROYER JR ROBERT J

Method and system for managing a NAND flash memory by paging segments of a logical to physical address map to a non-volatile memory

Drive assisted system checkpointing via system restore points

Cache write integrity logging

Delta checkpoints for a non-volatile memory indirection table

MANGOLD RICHARD P

Solid state drive management in power loss recovery

AKERS JASON B

Architectures and techniques for providing low-power storage mechanisms

RATN PRASUN

Optimized cold boot for non-volatile memory