Inventor

EDELSTEIN DANIEL CHARLES

US42 patents

⚠️ This page may combine multiple inventors who share the name “EDELSTEIN DANIEL CHARLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EDELSTEIN DANIEL CHARLES

IBM

Copper interconnection structure incorporating a metal seed layer

Integrated circuit spiral inductor

Apparatus and method for the electrochemical etching of a wafer

Method of forming an integrated circuit spiral inductor with ferromagnetic liner

Integrated circuit inductor

Integrated circuit toroidal inductor

Copper interconnection structure incorporating a metal seed layer

Method of making electroplated interconnection structures on integrated circuit chips

Method for forming Co-W-P-Au films

Silicon chip carrier with conductive through-vias and method for fabricating same

Thin metal barrier for electrical interconnections

Diamond-like carbon for use in VLSI and ULSI interconnect systems

Diamond-like carbon for use in VLSI and ULSI interconnect systems

Method for forming Co-W-P-Au films

Thin film metal barrier for electrical interconnections

Robust interconnect structure

Cu/low-k BEOL with nonconcurrent hybrid dielectric interface

Electroplating apparatus and method using a compressible contact

Voltage limiting circuit for fuse technology

Hybrid dielectric structure for improving the stiffness of back end of the line structures

Method and apparatus for single chamber treatment

Dual damascene horn antenna

Method for activating fusible links on a circuit substrate

BEOL decoupling capacitor

BEOL decoupling capacitor

Local interconnects having different material compositions

Recessed local interconnect semiconductor memory device

Dielectric fill for tight pitch MRAM pillar array

High-density memory devices using oxide gap fill

Contact via with pillar of alternating layers

Embedding magneto-resistive random-access memory devices between metal levels

Memory element with a hardmask stack having different stress levels

Backsides subtractive M1 patterning with backside contact repair for tight N2P space

Semiconductor backside transistor integration with backside power delivery network

Electrode with alloy interface

Electrode-via structure

Method and apparatus for single chamber treatment

Method and apparatus for single chamber treatment

Apparatus for activating fusible links on a circuit substrate

Sacrificial buffer layer for metal removal at a bevel edge of a substrate

Embedded metal contamination removal from BEOL wafers

INT BUSINESS MACHINES CORPORATION

Front end of line processing compatible thermally stable buried power rails