Inventor

CHERITON DAVID R

US99 patents

⚠️ This page may combine multiple inventors who share the name “CHERITON DAVID R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHERITON DAVID R

CHERITON DAVID R

Hardware-protected reference count-based memory management using weak references

Tunneled security groups

Hierarchical immutable content-addressable memory processor

Structured memory coprocessor

Hierarchical immutable content-addressable memory processor

Hierarchical immutable content-addressable memory processor

Memory sharing and page deduplication using indirect lines

Merge-update for efficient atomic memory modification in concurrent computer systems

Method and apparatus for processing duplicate packets

Hardware-supported per-process metadata tags

Retransmission and flow control in a logical network tunnel

Hierarchical associative memory-based classification system

Tunneled security groups

Interpreter-based program language translator using embedded interpreter types and variables

Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network

Efficient automated translation of procedures in constraint-based language

CISCO TECH INC

Retransmission and flow control in a logical network tunnel

Using ternary and binary content addressable memory stages to classify information such as packets

Method and apparatus for ingress port filtering for packet switching systems

System and method using hierarchical parallel banks of associative memories

Packet processing engine architecture

Per-flow dynamic buffer management

M-trie based packet processing

Redirecting multiple requests received over a connection to multiple servers and merging the responses over the connection

Hierarchical associative memory-based classification system

Method and apparatus for securing a communications device using a logging module

TCP optimized single rate policer

Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network

Method and apparatus for securing a communications device using a logging module

Method, apparatus and computer program product for borrowed-virtual-time scheduling

Approximated per-flow rate limiting

CISCO TECH IND

Approximated per-flow rate limiting

Protocol-independent support of remote DMA

Per-flow dynamic buffer management

Access control list processing in hardware

Method and apparatus for using ternary and binary content-addressable memory stages to classify packets

Dynamic behavioral queue classification and weighting

Network address translation for multicast virtual sourcing

Single-chip architecture for shared-memory router

Per-flow dynamic buffer management

Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network

TCP optimized single rate policer

HICAMP SYSTEMS INC

Hierarchical immutable content-addressable memory processor

Hierarchical immutable content-addressable memory processor

Hierarchical immutable content-addressable memory coprocessor

UNIV LELAND STANFORD JUNIOR

Cache memory for efficient data logging

Cache memory containing extra status bits to indicate memory regions where logging of data should occur

INTEL CORP

Hierarchical immutable content-addressable memory processor

Fine grained online remapping to handle memory errors

CISCO SYSTEMS INC

Method for traffic management, traffic prioritization, access control, and packet forwarding in a datagram computer network