Inventor
MEI CHUNHUI
US17 patents
⚠️ This page may combine multiple inventors who share the name “MEI CHUNHUI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
8 patentsUS9652284B2May 16, 2017
GPU divergence barrier
QUALCOMM INC18 citations83
US10026145B2Jul 17, 2018
Resource sharing on shader processor of GPU
QUALCOMM INC10 citations81
US9679347B2Jun 13, 2017
Shader pipeline with shared data channels
QUALCOMM INC5 citations73
US9569811B2Feb 14, 2017
Rendering graphics to overlapping bins
QUALCOMM INC6 citations72
US9123168B2Sep 1, 2015
Output ordering of domain coordinates for tessellation
QUALCOMM INC3 citations61
US10089708B2Oct 2, 2018
Constant multiplication with texture unit of graphics processing unit
QUALCOMM INC0 citations41
US9626762B2Apr 18, 2017
Stochastic rasterization using enhanced stencil operations on a graphics processing unit (GPU)
QUALCOMM INC0 citations41
US10504462B2Dec 10, 2019
Non-linear processing of two-dimensional data
QUALCOMM INC0 citations40
INTEL CORP
8 patentsUS11977885B2May 7, 2024
Utilizing structured sparsity in systolic arrays
INTEL CORP2 citations72
US12189571B2Jan 7, 2025
Dual pipeline parallel systolic array
INTEL CORP1 citations63
US12405787B2Sep 2, 2025
Utilizing structured sparsity in systolic arrays
INTEL CORP0 citations61
US12585590B2Mar 24, 2026
Broadcast asynchronous loads to shared local memory
INTEL CORP0 citations59
US11494163B2Nov 8, 2022
Conversion hardware mechanism
INTEL CORP1 citations58
US12579012B2Mar 17, 2026
Forward progress guarantee using single-level synchronization at individual thread granularity
INTEL CORP0 citations52
US12086205B2Sep 10, 2024
Random sparsity handling in a systolic array
INTEL CORP0 citations52
US12596656B2Apr 7, 2026
Prefetch aware LRU cache replacement policy
INTEL CORP0 citations46