Inventor
VALERIO JAMES
US28 patents
Patents
28 patentsUS4823260AApr 18, 1989
Mixed-precision floating point operations from a single instruction opcode
INTEL CORP66 citations94
US12182062B1Dec 31, 2024
Multi-tile memory management
INTEL CORP2 citations84
US11157283B2Oct 26, 2021
Instruction prefetch based on thread dispatch commands
INTEL CORP5 citations84
US10802967B1Oct 13, 2020
Partial write management in a multi-tiled compute engine
INTEL CORP7 citations84
US12561276B2Feb 24, 2026
Systems and methods for updating memory side caches in a multi-GPU configuration
INTEL CORP0 citations73
US12099461B2Sep 24, 2024
Multi-tile memory management
INTEL CORP0 citations73
US12554674B2Feb 17, 2026
Multi-tile memory management
INTEL CORP0 citations72
US10402224B2Sep 3, 2019
Microcontroller-based flexible thread scheduling launching in computing environments
INTEL CORP2 citations72
US11074109B2Jul 27, 2021
Dynamic load balancing of compute assets among different compute contexts
INTEL CORP5 citations71
US12014183B2Jun 18, 2024
Base plus offset addressing for load/store messages
INTEL CORP2 citations69
US12124852B2Oct 22, 2024
Instruction prefetch based on thread dispatch commands
INTEL CORP0 citations62
US11762662B2Sep 19, 2023
Instruction prefetch based on thread dispatch commands
INTEL CORP0 citations62
US11481864B2Oct 25, 2022
Workload scheduling and distribution on a distributed graphics device
INTEL CORP0 citations62
US11301384B2Apr 12, 2022
Partial write management in a multi-tiled compute engine
INTEL CORP0 citations62
US11288191B1Mar 29, 2022
Range based flushing mechanism
INTEL CORP0 citations62
US11175949B2Nov 16, 2021
Microcontroller-based flexible thread scheduling launching in computing environments
INTEL CORP0 citations62
US10997686B2May 4, 2021
Workload scheduling and distribution on a distributed graphics device
INTEL CORP1 citations62
US11977895B2May 7, 2024
Hierarchical thread scheduling based on multiple barriers
INTEL CORP1 citations61
US11726826B2Aug 15, 2023
Dynamic load balancing of compute assets among different compute contexts
INTEL CORP0 citations61
US12333310B2Jun 17, 2025
Base plus offset addressing for load/store messages
INTEL CORP0 citations59
US12164952B2Dec 10, 2024
Barrier state save and restore for preemption in a graphics environment
INTEL CORP0 citations59
US12579012B2Mar 17, 2026
Forward progress guarantee using single-level synchronization at individual thread granularity
INTEL CORP0 citations52
US12487824B2Dec 2, 2025
Immediate offset of load store and atomic instructions
INTEL CORP0 citations52
US11409579B2Aug 9, 2022
Multiple independent synchonization named barrier within a thread group
INTEL CORP0 citations52
US11321262B2May 3, 2022
Interconnected systems fence mechanism
INTEL CORP0 citations52
US11194722B2Dec 7, 2021
Apparatus and method for improved cache utilization and efficiency on a many core processor
INTEL CORP0 citations45
US10796472B2Oct 6, 2020
Method and apparatus for simultaneously executing multiple contexts on a graphics engine
INTEL CORP0 citations41
US10776897B1Sep 15, 2020
System and method to support multiple walkers per command
INTEL CORP0 citations39