Inventor

PAL SUPRATIM

US50 patents

⚠️ This page may combine multiple inventors who share the name “PAL SUPRATIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAL SUPRATIM

INTEL CORP

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Software scoreboard information and synchronization

Computing efficient cross channel operations in parallel computing machines using systolic arrays

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Hierarchical general register file (GRF) for execution block

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Sparse matrix optimization mechanism

Sparse matrix optimization mechanism

Hierarchical general register file (GRF) for execution block

Utilizing structured sparsity in systolic arrays

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Recompiling GPU code based on spill/fill instructions and number of stall cycles

Instruction and logic for systolic dot product with accumulate

Control flow mechanism for execution of graphics processor instructions using active channel packing

Supporting 8-bit floating point format operands in a computing architecture

Register file for systolic array

Dual pipeline parallel systolic array

Hierarchical general register file (GRF) for execution block

Supporting 8-bit floating point format operands in a computing architecture

Systolic array of arbitrary physical and logical depth

Computing efficient cross channel operations in parallel computing machines using systolic arrays

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Computing efficient cross channel operations in parallel computing machines using systolic arrays

Register sharing mechanism to equally allocate disabled thread registers to active threads

Utilizing structured sparsity in systolic arrays

Instructions and logic for vector multiply add with zero skipping

Instruction and logic for systolic dot product with accumulate

Control flow mechanism for execution of graphics processor instructions using active channel packing

Instructions and logic for vector multiply add with zero skipping

Dynamic thread splitting having multiple instruction pointers for the same thread

Gathering payload from arbitrary registers for send messages in a graphics environment

Multiple register allocation sizes for threads

Compiler assisted register file write reduction

Compiler assisted register file write reduction

Register sharing mechanism

Large integer multiplication enhancements for graphics environment

Use of a single instruction set architecture (ISA) instruction for vector normalization

Use of a single instruction set architecture (ISA) instruction for vector normalization

Forward progress guarantee using single-level synchronization at individual thread granularity

Source operand read suppression for graphics processors

Using sparsity metadata to reduce systolic array power consumption

Systolic array having support for output sparsity

Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environment

Accumulator pooling mechanism

Software scoreboard information and synchronization

Instruction that performs a scatter write

Banked memory access efficiency by a graphics processor

GUPTA NIRAJ

Simplification of local contrast compensation by using weighted look-up table