Inventor

MALLICK SOUMMYA

US44 patents

⚠️ This page may combine multiple inventors who share the name “MALLICK SOUMMYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MALLICK SOUMMYA

IBM

Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order

Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization

Method and system for executing a program within a multiscalar processor by processing linked thread descriptors

Latency-based scheduling of instructions in a superscalar processor

Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution

Address translation buffer for data processing system emulation mode

Method and system for constructing a program including a navigation instruction

Indirect unconditional branches in data processing system emulation mode

Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache

System and method for reducing power consumption in an electronic circuit

Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction

Method and system for interrupt handling during emulation in a data processing system

Method and system for processing branch instructions during emulation in a data processing system

System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference

Method and system for emulating instructions by performing an operation directly using special-purpose register contents

Apparatus and method for reducing the number of rename registers required in the operation of a processor

Generation of unique address alias for memory disambiguation buffer to avoid false collisions

Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors

Processor and method for out-of-order execution of instructions based upon an instruction parameter

Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction

Method and system for performing an emulation context save and restore that is transparent to the operating system

System and method for reducing power consumption in an electronic circuit

Method and apparatus for correcting misaligned instruction data

Method and system of executing speculative store instructions in a parallel processing computer system

Method for implementing a four-way least recently used (LRU) mechanism in high-performance

Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions

Method and system for recoding noneffective instructions within a data processing system

Method for executing speculative load instructions in high-performance processors

Method and system for minimizing the number of cycles required to execute semantic routines

Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle

Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation

Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue

Method for executing instructions and execution unit instruction reservation table within an in-order completion processor

Method and system for efficiently fetching from cache during a cache fill operation

System and method for dispatching two instructions to the same execution unit in a single cycle

Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor

Method and apparatus for dynamic allocation of registers for intermediate floating-point results

Method and system for efficient rename buffer deallocation within a processor

Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register

Method and system for recording noneffective instructions within a data processing system

Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor

Processor and method for out-of-order completion of floating-point operations during load/store multiple operations

Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch

(unassigned)

Instruction dispatch queue for improved instruction cache to queue timing