Inventor

STAVE ERIC J

US45 patents

⚠️ This page may combine multiple inventors who share the name “STAVE ERIC J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STAVE ERIC J

MICRON TECHNOLOGY INC

Multi-layer lead frame for a semiconductor device

Adjustable I/O timing from externally applied voltage

Semiconductor buffer circuit with a transition delay circuit

Methods for on-die memory termination and memory devices and systems employing the same

Method and apparatus for controlling timing of digital components

Multi-layer lead frame for a semiconductor device

Multi-layer lead frame for a semiconductor device

Real time testing using on die termination (ODT) circuit

Semiconductor buffer circuit with a transition delay circuit

Semiconductor buffer circuit with a transition delay circuit

Multi-layer lead frame for a semiconductor device

Multi-layer lead frame for a semiconductor device

Voltage adjustment based on pending refresh operations

Methods for on-die memory termination and memory devices and systems employing the same

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

Methods for on-die memory termination and memory devices and systems employing the same

Apparatus and method for performing continuous time linear equalization on a command/address signal

Apparatuses for characterizing system channels and associated methods and systems

Methods for on-die memory termination and memory devices and systems employing the same

Methods for on-die memory termination and memory devices and systems employing the same

Real time testing using on die termination (ODT) circuit

Multi-layer lead frame for a semiconductor device

Pseudo variable resistor for tester platform

Semiconductor buffer circuit with a transition delay circuit

Voltage adjustment based on pending refresh operations

Test devices having parallel impedances to reduce measurement input impedance and related apparatuses, systems, and methods

On-die termination configuration for a memory device

Apparatus with data-rate-based voltage control mechanism and methods for operating the same

Methods for triggering oscilloscopes and oscilloscopes employing the same

Methods for memory power management and memory devices and systems employing the same

Addressing scheme for a memory system

Apparatus with data-rate-based voltage control mechanism and methods for operating the same

Timing of read and write operations to reduce interference, and related devices, systems, and methods

Memory with per pin input/output termination and driver impedance calibration

Addressing scheme for a memory system

Self-calibration in a memory device

Methods for tuning command/address bus timing and memory devices and memory systems using the same

Methods for tuning command/address bus timing and memory devices and memory systems using the same

Power management for a memory device

Systems and techniques for jitter reduction

Interposers for memory device testing and characterization, including interposers for testing and characterizing decision feedback equalization circuitry of DDR5 memory devices

LODESTAR LICENSING GROUP LLC

Apparatus with data-rate-based voltage control mechanism and methods for operating the same

Methods for memory power management and memory devices and systems employing the same

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

NANYA TECHNOLOGY CORP

Data pattern generation for I/O training and characterization