Inventor

KRAUSE GUNNAR

DE29 patents

⚠️ This page may combine multiple inventors who share the name “KRAUSE GUNNAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRAUSE GUNNAR

INFINEON TECHNOLOGIES AG

System for testing fast synchronous semiconductor circuits

Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested

System for testing fast integrated digital circuits, in particular semiconductor memory modules

DDR to SDR conversion that decodes read and write accesses and forwards delayed commands to first and second memory modules

Semiconductor component and method for testing and operating a semiconductor component

Test circuit for testing a synchronous memory circuit

Method and device for offset-voltage free voltage measurement and adjustment of a reference voltage source of an integrated semiconductor circuit

Test circuit for testing a circuit

Address generator for generating addresses for an on-chip trim circuit

Method for on-chip testing of memory cells of an integrated memory circuit

Fuse configuration for a semiconductor storage device

Method and probe card configuration for testing a plurality of integrated circuits in parallel

Circuit configuration for the burn-in test of a semiconductor module

System for testing fast synchronous digital circuits, particularly semiconductor memory chips

Test data generator

Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices

Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits

Device and method for calibrating the pulse duration of a signal source

Circuit configuration having a variable number of data outputs and device for reading out data from the circuit configuration with the variable number of data outputs

Method of programming a semiconductor memory

Method and device for generating digital signal patterns

Address generator for generating addresses for testing a circuit

SIEMENS AG

Adjustable delay circuit

Integrated circuit with two operating states

Dynamic semiconductor memory device and method for initializing a dynamic semiconductor memory device

Selectively deactivating a first control loop in a dual control loop circuit during data transmission

(unassigned)

Test circuit

INFINEON TECHNOLOGIES

Method for determining the temperature of a semiconductor chip and semiconductor chip with temperature measuring configuration

INFINEON TECHOLOGIES AG

Test configuration and test method for testing a plurality of integrated circuits in parallel