Inventor

KHAN IMRAN

US70 patents

⚠️ This page may combine multiple inventors who share the name “KHAN IMRAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHAN IMRAN

TEXAS INSTRUMENTS INC

MOS transistors having higher drain current without reduced breakdown voltage

Merged bipolar and CMOS circuit and method

JFET structure for integrated circuit and fabrication method

Integrated circuit capacitor and method

N-channel demos device

Low cost fabrication method for high voltage, high drain current MOS transistor

Low noise JFET

JFET structure for integrated circuit and fabrication method

Memory device with reduced cell size

P-channel DEMOS device

P-channel DEMOS device

Zero temperature coefficient capacitor

SQUARE INC

Order fulfillment and tracking systems and methods

Order fulfillment and tracking systems and methods

Smart inventory tags

Extensible timer for chip card communications

Multi-device point-of-sale system having multiple customer-facing devices

Multi-functionality customer-facing device

Securely updating software on connected electronic devices

BLOCK INC

Multi-device point-of-sale system having multiple merchant-facing devices

Temporarily provisioning functionality in a multi-device point-of-sale system

Temporarily provisioning functionality in a multi-device point-of-sale system

Securely updating software on connected electronic devices

FIRST SOLAR INC

Photovoltaic device including a back contact and method of manufacturing

Photovoltaic device including a back contact and method of manufacturing

System and method for photovoltaic device temperature control while conditioning a photovoltaic device

Electrical bias methods and apparatus for photovoltaic device manufacture

EMC CORP

Technique for integrating VTL tape pools with MTree quotas

VTL adaptive commit

VTL adaptive commit

ADVANCED MICRO DEVICES INC

System and method for charge restoration in a non-volatile memory device

Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process

Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process

TRUATA LTD

System and method for objective quantification and mitigation of privacy risk

System and method for objective quantification and mitigation of privacy risk

System and method for guiding privacy-enhancing transformations

CHARLES STARK DRAPER LABORATORY INC

Wireless network for sensor array

Wireless network for sensor array

SPANSION LLC

Method to obtain multiple gate thicknesses using in-situ gate etch mask approach

Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant

GLOECKLER MARKUS

Photovoltaic module manufacture

BANK OF AMERICA

Software development system

SCHNEIDER ELECTRIC USA INC

Semantic search method for a distributed data system with numerical time series data

(unassigned)

Gene deleted recombinant FeLV proviral DNA for production of vaccines against FeLV

VERISHOP INC

Online multi-user shopping

LIN CHUAN

Controlling the latchup effect

VIEW INC

Adhesive bus bars in electrochromic windows

TEXAS INSTRUMENTS DEUTSCHLAND

EEPROM with reduced manufacturing complexity

UNIV NAT TSING HUA

Catalyst for generating hydrogen peroxide induced by temperature difference and method for environmental disinfection using same

CYPRESS SEMICONDUCTOR CORP

Controlling the latchup effect