Inventor
SURICO STEFANO
IT23 patents
⚠️ This page may combine multiple inventors who share the name “SURICO STEFANO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ATMEL CORP
15 patentsUS7417904B2Aug 26, 2008
Adaptive gate voltage regulation
ATMEL CORP35 citations92
US7414891B2Aug 19, 2008
Erase verify method for NAND-type flash memories
ATMEL CORP16 citations92
US7158415B2Jan 2, 2007
System for performing fast testing during flash reference cell setting
ATMEL CORP21 citations92
US7249215B2Jul 24, 2007
System for configuring parameters for a flash memory
ATMEL CORP26 citations91
US7181565B2Feb 20, 2007
Method and system for configuring parameters for flash memory
ATMEL CORP21 citations91
US7302518B2Nov 27, 2007
Method and system for managing a suspend request in a flash memory
ATMEL CORP8 citations71
US7769943B2Aug 3, 2010
Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory
ATMEL CORP2 citations62
US7570519B2Aug 4, 2009
Method and system for program pulse generation during programming of nonvolatile electronic devices
ATMEL CORP4 citations62
US7589572B2Sep 15, 2009
Method and device for managing a power supply power-on sequence
ATMEL CORP3 citations60
US7525856B2Apr 28, 2009
Apparatus and method to manage external voltage for semiconductor memory testing with serial interface
ATMEL CORP3 citations60
US7864583B2Jan 4, 2011
Erase verify for memory devices
ATMEL CORP3 citations54
US7551498B2Jun 23, 2009
Implementation of column redundancy for a flash memory with a high write parallelism
ATMEL CORP0 citations51
US7345921B2Mar 18, 2008
Method and system for a programming approach for a nonvolatile electronic device
ATMEL CORP1 citations51
US7447071B2Nov 4, 2008
Low voltage column decoder sharing a memory array p-well
ATMEL CORP0 citations41
US7404049B2Jul 22, 2008
Method and system for managing address bits during buffered program operations in a memory device
ATMEL CORP0 citations41
SURICO STEFANO
3 patentsUS8120963B2Feb 21, 2012
Method and system for program pulse generation during programming of nonvolatile electronic devices
SURICO STEFANO1 citations59
US8553460B2Oct 8, 2013
Method and system for program pulse generation during programming of nonvolatile electronic devices
SURICO STEFANO0 citations48
US8456917B1Jun 4, 2013
Logic circuit for a semiconductor memory device, and method of managing an operation in the semiconductor memory device
SURICO STEFANO0 citations45
ST MICROELECTRONICS SRL
2 patentsUS7284144B2Oct 16, 2007
Finite state machine interface has arbitration structure to store command generated by internal circuits during evaluation phase of state machine for FLASH EEPROM device
ST MICROELECTRONICS SRL8 citations73
US6981107B2Dec 27, 2005
Fast programming method for nonvolatile memories, in particular flash memories, and relative memory architecture
ST MICROELECTRONICS SRL1 citations50