Inventor

BHARDWAJ SARVESH

US4 patents

⚠️ This page may combine multiple inventors who share the name “BHARDWAJ SARVESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHARDWAJ SARVESH

2 patents

US8434040B2Apr 30, 2013

Clock-reconvergence pessimism removal in hierarchical static timing analysis

BHARDWAJ SARVESH2 citations57

US8775855B2Jul 8, 2014

Reducing memory used to store totals in static timing analysis

BHARDWAJ SARVESH1 citations45

UNIV ARIZONA

1 patent

US7630852B1Dec 8, 2009

Method of evaluating integrated circuit system performance using orthogonal polynomials

UNIV ARIZONA13 citations81

SYNOPSYS INC

1 patent

US8813011B2Aug 19, 2014

Clock-reconvergence pessimism removal in hierarchical static timing analysis

SYNOPSYS INC4 citations71