Inventor

FAUE JON ALLAN

US36 patents

⚠️ This page may combine multiple inventors who share the name “FAUE JON ALLAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAUE JON ALLAN

PROMOS TECHNOLOGIES INC

Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices

Pre-biased voltage level shifting circuit for integrated circuit devices utilizing differing power supply levels

Programmable latch circuit inserted into write data path of an integrated circuit memory

Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels

Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory device

Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section

Limited variable width internal clock generation

Dual equalization devices for long data line pairs

Low voltage differential amplifier circuit for wide voltage range operation

Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM

Efficient register for additive latency in DDR2 mode of operation

Tri-mode clock generator to control memory array access

Tri-mode clock generator to control memory array access

Reduced device count level shifter with power savings

UNITED MEMORIES INC

Pad input select circuit for use with bond options

Fast voltage regulation without overshoot

Fast voltage regulation without overshoot

Synchronous integrated circuit device utilizing an integrated clock/command technique

Apparatus, and associated method, for preventing occurrence of latch-up in an electronic circuit

Linear progression delay register

Linear progression delay register

Dual-complementary integrating duty cycle detector with dead band noise rejection

MOSEL VITELIC INC

System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM)

Arbitration method and circuit for control of integrated circuit double data rate (DDR) memory device output first-in, first-out (FIFO) registers

Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices

Integrated clocking latency and multiplexer control technique for double data rate (DDR) synchronous dynamic random access memory (SDRAM) device data paths

System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line

Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices

Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices

PROMOS TECHNOLOGIES PTE LTD

Using differential data strobes in non-differential mode to enhance data capture window

Data sorting in memories

Asymetric data path position and delays technique enabling high speed access in integrated circuit memory devices

Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks

Wide window clock scheme for loading output FIFO registers

NIPPON STEEL SEMICONDUCTOR

Current sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory device

UNITED MICROELECTRONICS CORP

High speed output enable path and method for an integrated circuit device