Inventor
KAMPF FRANCIS A
US22 patents
⚠️ This page may combine multiple inventors who share the name “KAMPF FRANCIS A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS6657565B2Dec 2, 2003
Method and system for improving lossless compression efficiency
IBM56 citations96
US6337852B1Jan 8, 2002
Flow control system using control information of a message for initiating retransmission of data portion when buffer is available
IBM47 citations96
US6480897B1Nov 12, 2002
Optimistic transmission flow control including receiver data discards upon inadequate buffering condition
IBM18 citations92
US6281816B1Aug 28, 2001
Method and apparatus for reducing data expansion during data compression
IBM26 citations92
US6271775B1Aug 7, 2001
Method for reducing data expansion during data compression
IBM23 citations92
US7085993B2Aug 1, 2006
System and method for correcting timing signals in integrated circuits
IBM38 citations91
US7251794B2Jul 31, 2007
Simulation testing of digital logic circuit designs
IBM30 citations88
US6338091B1Jan 8, 2002
System for optimistic transmission flow control including receiver data discards upon inadequate buffering condition
IBM6 citations73
US6105071AAug 15, 2000
Source and destination initiated interrupt system for message arrival notification
IBM14 citations73
US6098105AAug 1, 2000
Source and destination initiated interrupt method for message arrival notification
IBM13 citations73
US6098104AAug 1, 2000
Source and destination initiated interrupts for message arrival notification, and related data structures
IBM2 citations62
US7444258B2Oct 28, 2008
Automated simulation testbench generation for serializer/deserializer datapath systems
IBM2 citations61
US7113488B2Sep 26, 2006
Reconfigurable circular bus
IBM5 citations60
US7360138B2Apr 15, 2008
Verification of the design of an integrated circuit background
IBM2 citations55
US7286770B2Oct 23, 2007
Fiber optic transmission lines on an SOC
IBM2 citations48
US7831879B2Nov 9, 2010
Generating test coverage bin based on simulation result
IBM1 citations43
US7139881B2Nov 21, 2006
Semiconductor device comprising a plurality of memory structures
IBM0 citations41
US7480607B2Jan 20, 2009
Circuit design verification
IBM0 citations33