Inventor

TIRUMALAI PARTHA P

US32 patents

⚠️ This page may combine multiple inventors who share the name “TIRUMALAI PARTHA P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TIRUMALAI PARTHA P

SUN MICROSYSTEMS INC

Method and apparatus for automatic selection of the load latency to be used in modulo scheduling in an optimizing compiler

Locked prefetch scheduling in general cyclic regions

Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions

Method and apparatus for optimizing computer program performance using steered execution

Microprocessor having a page prefetch cache for database applications

Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler

Using tiling to improve performance in a sparse symmetric direct matrix solver

Method for employing a page prefetch cache for database applications

Method and apparatus for inserting prefetch instructions in an optimizing compiler

Method and apparatus for selecting references for prefetching in an optimizing compiler

Hybrid technique for performing a column modification operation in a sparse symmetric direct matrix solver

Method and apparatus for simultaneous optimization of code targeting multiple machines

Method and system for generating prefetch information for multi-block indirect memory access chains

Method and system for identifying multi-block indirect memory access chains

SONG YONGHONG

Compiler framework for speculative automatic parallelization with transactional memory

Parallelizing non-countable loops with hardware transactional memory

Static profitability control for speculative automatic parallelization

Pipelined parallelization with localized self-helper threading

Controlling and dynamically varying automatic parallelization

Value predictable variable scoping for speculative automatic parallelization with transactional memory

Fault tolerant compilation with automatic error correction

Fault tolerant compilation with automatic optimization adjustment

Method and system for interprocedural prefetching

KALOGEROPULOS SPIROS

Minimizing register spills by using register moves

Compiler implementation of lock/unlock using hardware transactional memory

Method and system for utilizing parallelism across loops

ORACLE AMERICA INC

Facilitating communication and synchronization between main and scout threads

Runtime profitability control for speculative automatic parallelization

Method and apparatus for software scouting regions of a program

TIRUMALAI PARTHA P

Anticipatory helper thread based code execution

Adaptive code through self steered execution

ORACLE INT CORP

Platform specific optimizations in static compilers