P

Inventor

XIE JIANYONG

CN37 patents
⚠️ This page may combine multiple inventors who share the name “XIE JIANYONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

29 patents
US10847467B2Nov 24, 2020

Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same

INTEL CORP21 citations94
US11621227B2Apr 4, 2023

Power delivery for embedded bridge die utilizing trench structures

INTEL CORP6 citations86
US11222848B2Jan 11, 2022

Power delivery for embedded bridge die utilizing trench structures

INTEL CORP6 citations86
US10950550B2Mar 16, 2021

Semiconductor package with through bridge die connections

INTEL CORP10 citations86
US11837549B2Dec 5, 2023

Power delivery for embedded bridge die utilizing trench structures

INTEL CORP3 citations84
US12062616B2Aug 13, 2024

Power delivery for embedded bridge die utilizing trench structures

INTEL CORP2 citations73
US11817391B2Nov 14, 2023

Power delivery for embedded bridge die utilizing trench structures

INTEL CORP3 citations73
US11728294B2Aug 15, 2023

Capacitor die embedded in package substrate for providing capacitance to surface mounted die

INTEL CORP1 citations73
US10490503B2Nov 26, 2019

Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same

INTEL CORP4 citations73
US11276635B2Mar 15, 2022

Horizontal pitch translation using embedded bridge dies

INTEL CORP2 citations71
US12538823B2Jan 27, 2026

Power delivery for embedded bridge die utilizing trench structures

INTEL CORP0 citations62
US12205924B2Jan 21, 2025

Semiconductor packages with chiplets coupled to a memory device

INTEL CORP0 citations62
US12046568B2Jul 23, 2024

Capacitor die embedded in package substrate for providing capacitance to surface mounted die

INTEL CORP0 citations62
US11887932B2Jan 30, 2024

Dielectric-filled trench isolation of vias

INTEL CORP0 citations62
US11621223B2Apr 4, 2023

Interconnect hub for dies

INTEL CORP1 citations62
US11610862B2Mar 21, 2023

Semiconductor packages with chiplets coupled to a memory device

INTEL CORP1 citations62
US11545416B2Jan 3, 2023

Minimization of insertion loss variation in through-silicon vias (TSVs)

INTEL CORP0 citations62
US11462521B2Oct 4, 2022

Multilevel die complex with integrated discrete passive components

INTEL CORP0 citations62
US11296031B2Apr 5, 2022

Dielectric-filled trench isolation of vias

INTEL CORP0 citations62
US11222837B2Jan 11, 2022

Low-inductance current paths for on-package power distributions and methods of assembling same

INTEL CORP0 citations62
US11195805B2Dec 7, 2021

Capacitor die embedded in package substrate for providing capacitance to surface mounted die

INTEL CORP0 citations62
US11114394B2Sep 7, 2021

Signal routing carrier

INTEL CORP0 citations62
US10651117B2May 12, 2020

Low-inductance current paths for on-package power distributions and methods of assembling same

INTEL CORP1 citations62
US12057413B2Aug 6, 2024

Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost

INTEL CORP0 citations61
US11694952B2Jul 4, 2023

Horizontal pitch translation using embedded bridge dies

INTEL CORP0 citations61
US11387187B2Jul 12, 2022

Embedded very high density (VHD) layer

INTEL CORP0 citations60
US11456281B2Sep 27, 2022

Architecture and processes to enable high capacity memory packages through memory die stacking

INTEL CORP1 citations58
US12218063B2Feb 4, 2025

EMIB architecture with dedicated metal layers for improving power delivery

INTEL CORP0 citations56
US12341129B2Jun 24, 2025

Substrateless double-sided embedded multi-die interconnect bridge

INTEL CORP0 citations50

PETROCHINA CO LTD

4 patents

UNIV SOUTHWEST PETROLEUM

1 patent

XIE JIANYONG

1 patent

UNIV LANZHOU

1 patent

LI QINGENG

1 patent