P

Inventor

WANG ZHIHAI

CN44 patents
⚠️ This page may combine multiple inventors who share the name “WANG ZHIHAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI LOGIC CORP

22 patents
US6028015AFeb 22, 2000

Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption

LSI LOGIC CORP173 citations99
US6881664B2Apr 19, 2005

Process for planarizing upper surface of damascene wiring structure for integrated circuit structures

LSI LOGIC CORP75 citations98
US5660682AAug 26, 1997

Plasma clean with hydrogen gas

LSI LOGIC CORP100 citations98
US6727177B1Apr 27, 2004

Multi-step process for forming a barrier film for use in copper layer formation

LSI LOGIC CORP58 citations96
US5770520AJun 23, 1998

Method of making a barrier layer for via or contact opening of integrated circuit structure

LSI LOGIC CORP57 citations96
US5902129AMay 11, 1999

Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers

LSI LOGIC CORP87 citations95
US6368979B1Apr 9, 2002

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure

LSI LOGIC CORP52 citations92
US6204550B1Mar 20, 2001

Method and composition for reducing gate oxide damage during RF sputter clean

LSI LOGIC CORP20 citations92
US6010952AJan 4, 2000

Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation

LSI LOGIC CORP24 citations92
US5994211ANov 30, 1999

Method and composition for reducing gate oxide damage during RF sputter clean

LSI LOGIC CORP20 citations92
US5874342AFeb 23, 1999

Process for forming MOS device in integrated circuit structure using cobalt silicide contacts as implantation media

LSI LOGIC CORP69 citations92
US6174798B1Jan 16, 2001

Process for forming metal interconnect stack for integrated circuit structure

LSI LOGIC CORP15 citations83
US6734560B2May 11, 2004

Diamond barrier layer

LSI LOGIC CORP6 citations74
US6472314B1Oct 29, 2002

Diamond barrier layer

LSI LOGIC CORP12 citations74
US6736953B1May 18, 2004

High frequency electrochemical deposition

LSI LOGIC CORP8 citations73
US6569751B1May 27, 2003

Low via resistance system

LSI LOGIC CORP9 citations73
US6087726AJul 11, 2000

Metal interconnect stack for integrated circuit structure

LSI LOGIC CORP14 citations73
US7081406B2Jul 25, 2006

Interconnect dielectric tuning

LSI LOGIC CORP4 citations63
US6767832B1Jul 27, 2004

In situ liner barrier

LSI LOGIC CORP5 citations63
US6489231B1Dec 3, 2002

Method for forming barrier and seed layer

LSI LOGIC CORP3 citations57
US6893962B2May 17, 2005

Low via resistance system

LSI LOGIC CORP0 citations51
US6518193B1Feb 11, 2003

Substrate processing system

LSI LOGIC CORP0 citations37

MAXIM INTEGRATED PRODUCTS

7 patents

KERNESS NICOLE D

4 patents

LSI CORP

3 patents

LUXTRON CORP

1 patent

HOLENARSIPUR PRASHANTH

1 patent

WANG ZHIHAI

1 patent

HU YING

1 patent

LEADWAY HK LTD

1 patent

HANGZHOU HIKVISION DIGITAL TEC

1 patent

LI ZHIJUN

1 patent

GUO WENJIE

1 patent