Inventor
KINOSHITA HIRO
US13 patents
⚠️ This page may combine multiple inventors who share the name “KINOSHITA HIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SPANSION LLC
5 patentsUS7943983B2May 17, 2011
HTO offset spacers and dip off process to define junction
SPANSION LLC3 citations58
US8012830B2Sep 6, 2011
ORO and ORPRO with bit line trench to suppress transport program disturb
SPANSION LLC0 citations52
US7935596B2May 3, 2011
HTO offset and BL trench process for memory device to improve device performance
SPANSION LLC0 citations51
US7906807B2Mar 15, 2011
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
SPANSION LLC0 citations51
US7776688B2Aug 17, 2010
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
SPANSION LLC0 citations51
CHENG NING
3 patentsUS8653581B2Feb 18, 2014
HTO offset for long Leffective, better device performance
CHENG NING7 citations83
US9245895B2Jan 26, 2016
Oro and orpro with bit line trench to suppress transport program disturb
CHENG NING0 citations51
US8330209B2Dec 11, 2012
HTO offset and BL trench process for memory device to improve device performance
CHENG NING0 citations51
SANDISK TECHNOLOGIES LLC
2 patentsUS10121794B2Nov 6, 2018
Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof
SANDISK TECHNOLOGIES LLC33 citations91
US9985046B2May 29, 2018
Method of forming a staircase in a semiconductor device using a linear alignment control feature
SANDISK TECHNOLOGIES LLC17 citations86