Inventor
GRAEF NILS
US33 patents
⚠️ This page may combine multiple inventors who share the name “GRAEF NILS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GRAEF NILS
15 patentsUS8161345B2Apr 17, 2012
LDPC decoders using fixed and adjustable permutators
GRAEF NILS46 citations94
US8098451B2Jan 17, 2012
Systems and methods for variable fly height measurement
GRAEF NILS32 citations92
US8797795B2Aug 5, 2014
Methods and apparatus for intercell interference mitigation using modulation coding
GRAEF NILS5 citations84
US8578256B2Nov 5, 2013
Low-latency decoder
GRAEF NILS15 citations84
US8484535B2Jul 9, 2013
Error-floor mitigation of codes using write verification
GRAEF NILS14 citations84
US8503128B2Aug 6, 2013
Systems and methods for variable compensated fly height measurement
GRAEF NILS2 citations62
US8196002B2Jun 5, 2012
Systems and methods for joint LDPC encoding and decoding
GRAEF NILS2 citations62
US8161348B2Apr 17, 2012
Systems and methods for low cost LDPC decoding
GRAEF NILS4 citations62
US7640444B2Dec 29, 2009
Systems and methods for low power bus operation
GRAEF NILS3 citations62
US8077812B2Dec 13, 2011
Reduced-complexity multiple-input, multiple-output detection
GRAEF NILS2 citations53
US9753877B2Sep 5, 2017
Memory read-channel with signal processing on general purpose processor
GRAEF NILS0 citations52
US9544090B2Jan 10, 2017
Hard input low density parity check decoder
GRAEF NILS0 citations52
US9356623B2May 31, 2016
LDPC decoder variable node units having fewer adder stages
GRAEF NILS0 citations52
US8140947B2Mar 20, 2012
Method and apparatus for storing survivor paths in a Viterbi detector using systematic pointer exchange
GRAEF NILS1 citations52
US8250386B2Aug 21, 2012
Turning off buffer when a digital back end operates at a same data rate as the analog front end
GRAEF NILS0 citations41
AGERE SYSTEMS INC
13 patentsUS7702989B2Apr 20, 2010
Systems and methods for generating erasure flags
AGERE SYSTEMS INC100 citations98
US7730384B2Jun 1, 2010
Method and apparatus for evaluating performance of a read channel
AGERE SYSTEMS INC47 citations97
US7971125B2Jun 28, 2011
Systems and methods for prioritizing error correction data
AGERE SYSTEMS INC28 citations92
US8014196B2Sep 6, 2011
Reduced-power programming of multi-level cell (MLC) memory
AGERE SYSTEMS INC17 citations84
US8032818B2Oct 4, 2011
Method and apparatus for storing survivor paths in a Viterbi detector using input-dependent pointer exchange
AGERE SYSTEMS INC2 citations63
US7876847B2Jan 25, 2011
Global minimum-based MLD demapping for soft-output MIMO detection
AGERE SYSTEMS INC2 citations63
US7707449B2Apr 27, 2010
Systems and methods for low power multi-rate data paths
AGERE SYSTEMS INC2 citations63
US7669110B2Feb 23, 2010
Trace-ahead method and apparatus for determining survivor paths in a Viterbi detector
AGERE SYSTEMS INC3 citations63
US7583762B2Sep 1, 2009
Reduced-complexity multiple-input, multiple-output detection
AGERE SYSTEMS INC4 citations63
US8046669B2Oct 25, 2011
Method and apparatus for evaluating performance of a read channel
AGERE SYSTEMS INC1 citations62
US7729075B2Jun 1, 2010
Low-power read channel for magnetic mass storage systems
AGERE SYSTEMS INC0 citations52
US7676001B2Mar 9, 2010
MLD demapping using sub-metrics for soft-output MIMO detection and the like
AGERE SYSTEMS INC0 citations52
US7941732B2May 10, 2011
Method and apparatus for evaluating performance of a read channel
AGERE SYSTEMS INC0 citations51