Inventor

DRERUP BERNARD C

US48 patents

⚠️ This page may combine multiple inventors who share the name “DRERUP BERNARD C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DRERUP BERNARD C

IBM

System and method for controlling data transfer between multiple interconnected computer systems with an untethered stylus

Descriptor prefetch mechanism for high latency and out of order DMA device

Converting a central arbiter to a slave arbiter for interconnected systems

System crash detect and automatic reset mechanism for processor cards

Method and apparatus for bus access allocation

Low latency cadence selectable interface for data transfers between busses of differing frequencies

Hybrid replacement policy in a multilevel cache memory hierarchy

Counter-based victim selection in a cache memory

Counter-based victim selection in a cache memory

Push instruction for pushing a message payload from a sending thread to a receiving thread

Hardware-assisted interthread push communication

Hardware-assisted interthread push communication

Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips

Barrier and interrupt mechanism for high latency and out of order DMA device

Method for performing a direct memory access block move in a direct memory access device

Transfer request pipeline throttling

Prefetch performance

Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread

Reducing snoop response time for snoopers without copies of requested data via snoop filtering

Reducing latency of a snoop tenure

Cache line replacement using reference states based on data reference attributes

Counter-based victim selection in a cache memory

Single request data transfer regardless of size and alignment

System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture

Controlling issue rates of requests of varying broadcast scopes in a data processing system

Distribution of injected data among caches of a data processing system

Data processing system having masters that adapt to agents with differing retry behaviors

Using idle caches as a backing store for boot code

Speculative delivery of data from a lower level of a memory hierarchy in a data processing system

Split transaction coherency protocol in a data processing system

Prefetch performance

Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread

Push instruction for pushing a message payload from a sending thread to a receiving thread

Structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization

Cluster-wide system clock in a multi-tiered full-graph interconnect architecture

Targeting of lateral castouts in a data processing system

Selective snooping by snoop masters to locate updated data

Selective snooping by snoop masters to locate updated data

Cache data replacement in a networked computing system using reference states based on reference attributes

Counter-based victim selection in a cache memory

Injection of at least a partial cache line in a private multilevel cache hierarchy

Single request data transfer regardless of size and alignment

Method of piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization

ARIMILLI LAKSHMINARAYANA B

Performing dynamic request routing based on broadcast queue depths

Collective acceleration unit tree flow control and retransmit

Collective acceleration unit tree structure

Collective acceleration unit tree structure

ARIMILLI LAKSHMINARAYANA

Synchronization optimized queuing system