Inventor

THOMANN MARK R

US36 patents

⚠️ This page may combine multiple inventors who share the name “THOMANN MARK R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THOMANN MARK R

MICRON TECHNOLOGY INC

CMOS bootstrapped output driver method and circuit

Method of reducing standby current during power down mode

Video random access memory device and method implementing independent two WE nibble control

Method of reducing standby current during power down mode

Delay locked loop control circuit

Read/write timing calibration of a memory array using a row or a redundant row

High speed I/O calibration using an input path and simplified logic

Expandable data width SAM for a multiport RAM

Circuit and method for decreasing the cell margin during a test mode

Video random access memory chip configured to transfer data in response to an internal write signal

Controller for delay locked loop circuits

Double data rate scheme for data output

Differential input buffer bias circuit

Expandable data width sam for a multiport ram

Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology

Memory device having complete row redundancy

Enhancement circuit and method for ensuring diactuation of a switching device

CMOS bootstrapped output driver method and circuit

Video random access memory device and method implementing independent two we nibble control

Delay locked loop control circuit

Method of reducing standby current during power down mode

Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology

Data transfer in a memory device having complete row redundancy

System having multiple subsystems and test signal source resident upon common substrate

Method and apparatus for testing a memory device with compressed data using a single output

Controller for delay locked loop circuits

Integrated circuit power-up controllers, integrated circuit power-up circuits, and integrated circuit power-up methods

Method and apparatus for enhanced booting and DC conditions

Method and apparatus for enhanced booting and DC conditions

Method and apparatus for enhanced booting and DC conditions

Method and apparatus for testing a memory device with compressed data using a single output

Double data rate scheme for data output

System having multiple subsystems and test signal source resident upon common substrate

Double data rate scheme for data output

MICRON SEMICONDUCTOR INC

Circuit and method for decreasing the cell margin during a test mode

Test signal generator on substrate to test