Inventor

KOUDELE LARRY J

US110 patents

⚠️ This page may combine multiple inventors who share the name “KOUDELE LARRY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOUDELE LARRY J

MICRON TECHNOLOGY INC

Memory device with dynamic program-verify voltage calibration

Memory system with dynamic calibration using a trim management mechanism

Memory device with dynamic program-verify voltage calibration

Memory device with dynamic processing level calibration

Memory quality monitor based compensation method and apparatus

Memory device with dynamic program-verify voltage calibration

Block family combination and voltage bin selection

Memory system with dynamic calibration using a variable adjustment mechanism

Voltage offset bin selection by die group for memory devices

Performing threshold voltage offset bin selection by package for memory devices

Memory system with dynamic calibration using a trim management mechanism

Dynamic programing of valley margins of a memory cell

Memory system with dynamic calibration using a variable adjustment mechanism

First-pass dynamic program targeting (DPT)

Providing data of a memory system based on an adjustable error rate

Memory device with dynamic programming calibration

Continuous adjusting of sensing voltages

Adjusting a parameter for a programming operation based on the temperature of a memory system

Block family-based error avoidance for memory devices

Open block family duration limited by time and temperature

Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

Open block family duration limited by temperature variation

Selection of read offset values in a memory sub-system

Error avoidance based on voltage distribution parameters of block families

Closing block family based on soft and hard closure criteria

Generating embedded data in memory cells in a memory sub-system

Dynamic program erase targeting with bit error rate

Dynamic temperature compensation in a memory component

Memory device with dynamic processing level calibration

Block family-based error avoidance for memory devices

Read level calibration in memory devices using embedded servo cells

Estimation of read level thresholds using a data structure

Dynamic background scan optimization in a memory sub-system

Dynamic temperature compensation in a memory component

Memory device with dynamic processing level calibration

Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution

Open block family duration limited by temperature variation

Block family-based error avoidance for memory devices

Open block family duration limited by time and temperature

Adjustment of a starting voltage corresponding to a program operation in a memory sub-system

Memory device with dynamic processing level calibration

Combination scan management for block families of a memory device

Memory device with dynamic program-verify voltage calibration

Selection of read offset values in a memory sub-system based on temperature and time to program levels

SEAGATE TECHNOLOGY

Track dependent variable level qualification pulse detector

Qualification for pulse detecting in a magnetic media data storage system

KOUDELE LARRY J

Advanced golf monitoring system, method and components

LIIKANEN BRUCE A

Memory quality monitor based compensation method and apparatus

MAXTOR CORP

Method and apparatus for high fly write detection in a disk drive

SQUIRES CHRISTOPHER J

Digital component power savings in a host device and method