Inventor

Pappu Lakshminarayana

US42 patents

⚠️ This page may combine multiple inventors who share the name “Pappu Lakshminarayana”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Pappu Lakshminarayana

INTEL CORP

Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package

Stacked semiconductor package and method for performing bare die testing on a functional die in a stacked semiconductor package

Memory controller management techniques for managing data transfer for memory access operations

System, apparatus and method for handshaking protocol for low power state transitions

Systems, methods, and apparatuses for implementing testing of a far memory subsystem within two-level memory (2LM) stacked die subsystems

Redundancy in distribution of voltage-frequency scaling parameters

Efficient low cost on-die configurable bridge controller

Systems, methods, and apparatuses for implementing a virtual device observation and debug network for high speed serial IOS

Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems

System, method, apparatus and architecture for dynamically configuring device fabrics

Dynamic voltage and frequency scaling for discrete graphics systems

Dynamically programmable memory test traffic router

Techniques in ensuring functional safety (fusa) systems

Platform debug and testing with secured hardware

Mechanism to provide back-to-back testing of memory controller operation

Methods and apparatus to reduce display connection latency

Device, system and method for providing on-chip test/debug functionality

System, apparatus and method for functional testing of one or more fabrics of a processor

Innovative high speed serial controller testing

Innovative high speed serial controller testing

System, apparatus and method for providing a fabric for an accelerator

System-on-a-chip (SoC) architecture for low power state communication

System, apparatus and method for inter-die functional testing of an integrated circuit

Modular GPU architecture for clients and servers

Low latency communication path for audio/visual (A/V) applications

Infrastructure for platform immersive experience

Touch host controller

Display controller testing through high speed communications switch

Protocol aware testing engine for high speed link integrity testing

Low cost inbuilt deterministic tester for SOC testing

Platform component interconnect testing

Maintaining IO block operation in electronic systems for board testing

Board level leakage testing for memory interface

Phase lock loop bypass for board-level testing of systems

Chip fabric interconnect quality on silicon

Serial I/O functional tester

Interconnect network for multi-tile system on chips

Atomic handling for disaggregated 3D structured SoCs

Device, system and method for packet processing to facilitate circuit testing

Firmware fingerprinting based on data monitored during firmware loading

Device, system and method for on-chip testing of protocol stack circuitry

Pappu Lakshminarayana

Apparatus and method for a scalable test engine