Inventor

SUE PIN-DAI

TW56 patents

⚠️ This page may combine multiple inventors who share the name “SUE PIN-DAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUE PIN-DAI

TAIWAN SEMICONDUCTOR MFG CO LTD

Transmission gate structure and method

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Power strap structure for high performance and low current density

Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits

Tie off device

Double rule integrated circuit layouts for a dual transmission gate

Method for manufacturing a cell having pins and semiconductor device based on same

Integrated circuit layout and method of configuring the same

Semiconductor device and layout design thereof

Transmission gate structure, layout, methods, and system

Double rule integrated circuit layouts for a dual transmission gate

Power strap structure for high performance and low current density

Double rule integrated circuit layouts for a dual transmission gate

Power strap structure for high performance and low current density

Integrated circuit and method of fabricating the same

Cell boundaries for self aligned multiple patterning abutments

Reduced area standard cell abutment configurations

Power switch circuit, IC structure of power switch circuit, and method of forming IC structure

Semiconductor device having fin structure

Method for manufacturing a cell having pins and semiconductor device based on same

Semiconductor device having fin structure

Semiconductor device and layout design thereof

Double rule integrated circuit layouts for a dual transmission gate

Integrated circuit and method of fabricating the same

Tie off device

Integrated circuit having fins crossing cell boundary

Reduced area standard cell abutment configurations

Method and system for generating layout diagram including wiring arrangement

System and method for generating layout diagram including wiring arrangement

Transmission gate structure

Isolation circuit between power domains

Integrated circuit having fins crossing cell boundary

System for generating layout diagram including wiring arrangement

Method for generating layout diagram including wiring arrangement

Transmission gate manufacturing method

Isolation circuit between power domains

Reduced area standard cell abutment configurations

Semiconductor device

Power switch circuit, IC structure of power switch circuit, and method of forming IC structure

Semiconductor device

Semiconductor device

Isolation circuit between power domains

Semiconductor device having fin structure

Semiconductor device and layout design thereof

Integrated circuit layout and method of configuring the same

Integrated circuit and method of fabricating the same

HOU YUNG-CHIN

Integrated circuit layouts with power rails under bottom metal layer

OU TSONG-HUA

Adaptive fin design for FinFETs

TAIWAN SEMICONDUCTOR MFG

Self-aligned multiple patterning layout design

YANG JEN-HANG

Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits