P

Inventor

BERNIER WILLIAM E

US29 patents
⚠️ This page may combine multiple inventors who share the name “BERNIER WILLIAM E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

21 patents
US6559666B2May 6, 2003

Method and device for semiconductor testing using electrically conductive adhesives

IBM80 citations98
US6425772B1Jul 30, 2002

Conductive adhesive having a palladium matrix interface between two metal surfaces

IBM59 citations94
US6550667B2Apr 22, 2003

Flux composition and soldering method for high density arrays

IBM17 citations92
US6288559B1Sep 11, 2001

Semiconductor testing using electrically conductive adhesives

IBM20 citations92
US4374001AFeb 15, 1983

Electrolytic printing

IBM38 citations92
US4444626AApr 24, 1984

Electrochromic printing

IBM32 citations90
US7566649B2Jul 28, 2009

Compressible films surrounding solder connectors

IBM8 citations83
US7170187B2Jan 30, 2007

Low stress conductive polymer bump

IBM11 citations82
US7119003B2Oct 10, 2006

Extension of fatigue life for C4 solder ball to chip connection

IBM14 citations80
US6268739B1Jul 31, 2001

Method and device for semiconductor testing using electrically conductive adhesives

IBM12 citations74
US7442878B2Oct 28, 2008

Low stress conductive polymer bump

IBM7 citations72
US7332821B2Feb 19, 2008

Compressible films surrounding solder connectors

IBM7 citations72
US6331119B1Dec 18, 2001

Conductive adhesive having a palladium matrix interface between two metal surfaces

IBM14 citations71
US7316572B2Jan 8, 2008

Compliant electrical contacts

IBM6 citations62
US6492071B1Dec 10, 2002

Wafer scale encapsulation for integrated flip chip and surface mount technology assembly

IBM4 citations62
US4453171AJun 5, 1984

Reduced electrode wear in electrolytic printing by pH control of the print reaction zone

IBM2 citations59
US10699972B2Jun 30, 2020

Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity

IBM0 citations51
US9899279B2Feb 20, 2018

Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity

IBM0 citations51
US6921015B2Jul 26, 2005

Solder protective coating and fluxless joining of flip chip devices on laminates with plated solder

IBM1 citations51
US6585150B1Jul 1, 2003

Solder protective coating and fluxless joining of flip chip devices on laminates with plated solder

IBM0 citations51
US7067916B2Jun 27, 2006

Extension of fatigue life for C4 solder ball to chip connection

IBM0 citations48

UNIV NEW YORK STATE RES FOUND

5 patents

BERNIER WILLIAM E

2 patents

SMITH GLEN A

1 patent