Inventor
LEI JUNJIANG
US27 patents
⚠️ This page may combine multiple inventors who share the name “LEI JUNJIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
11 patentsUS10671052B2Jun 2, 2020
Synchronized parallel tile computation for large area lithography simulation
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations79
US10990002B2Apr 27, 2021
Sub-resolution assist features
TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73
US10838305B2Nov 17, 2020
Lithographic mask correction using volume correction techniques
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations72
US11340584B2May 24, 2022
Synchronized parallel tile computation for large area lithography simulation
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations70
US10915090B2Feb 9, 2021
Synchronized parallel tile computation for large area lithography simulation
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations70
US12416857B2Sep 16, 2025
Sub-resolution assist features
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11829066B2Nov 28, 2023
Sub-resolution assist features
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12112116B2Oct 8, 2024
Machine learning based model builder and its applications for pattern transferring in semiconductor manufacturing
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11610043B2Mar 21, 2023
Machine learning based model builder and its applications for pattern transferring in semiconductor manufacturing
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations61
US11531273B2Dec 20, 2022
Lithographic mask correction using volume correction techniques
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11747786B2Sep 5, 2023
Synchronized parallel tile computation for large area lithography simulation
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations59
CADENCE DESIGN SYSTEMS INC
5 patentsUS8381152B2Feb 19, 2013
Method and system for model-based design and layout of an integrated circuit
CADENCE DESIGN SYSTEMS INC10 citations83
US7904853B1Mar 8, 2011
Pattern signature
CADENCE DESIGN SYSTEMS INC7 citations82
US7966586B2Jun 21, 2011
Intelligent pattern signature based on lithography effects
CADENCE DESIGN SYSTEMS INC8 citations81
US7631289B1Dec 8, 2009
Method and system for implementing optimized lithography models for accuracy and resolution
CADENCE DESIGN SYSTEMS INC5 citations62
US8358828B2Jan 22, 2013
Interpolation of irregular data in a finite-dimensional metric space in lithographic simulation
CADENCE DESIGN SYSTEMS INC0 citations38
MENTOR GRAPHICS CORP
4 patentsUS9836556B2Dec 5, 2017
Optical proximity correction for directed-self-assembly guiding patterns
MENTOR GRAPHICS CORP6 citations83
US8910098B1Dec 9, 2014
Neighbor-aware edge fragment adjustment for optical proximity correction
MENTOR GRAPHICS CORP10 citations78
US8881070B1Nov 4, 2014
Optical proximity correction based on edge fragment correlation
MENTOR GRAPHICS CORP3 citations62
US10311165B2Jun 4, 2019
Guiding patterns optimization for directed self-assembly
MENTOR GRAPHICS CORP0 citations51
LAI YA-CHIEH
3 patentsUS8079005B2Dec 13, 2011
Method and system for performing pattern classification of patterns in integrated circuit designs
LAI YA-CHIEH29 citations91
US8677301B2Mar 18, 2014
Method and system for model-based design and layout of an integrated circuit
LAI YA-CHIEH8 citations82
US8645887B2Feb 4, 2014
Method and system for model-based design and layout of an integrated circuit
LAI YA-CHIEH6 citations82