Inventor

KHARE PRASANNA

US49 patents

⚠️ This page may combine multiple inventors who share the name “KHARE PRASANNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHARE PRASANNA

ST MICROELECTRONICS INC

Method of forming a fully substrate-isolated FinFET transistor

FinFET device with isolated channel

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Method to co-integrate SiGe and Si channels for finFET devices

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

Fully substrate-isolated FinFET transistor

Bulk finFET semiconductor-on-nothing integration

Method to co-integrate SiGe and Si channels for finFET devices

Fully substrate-isolated FinFET transistor

Method to co-integrate SiGe and Si channels for finFET devices

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

Method for the formation of fin structures for FinFET devices

Method of making a semiconductor device including an all around gate

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Method of making a semiconductor device using a dummy gate

Method of making a semiconductor device using a dummy gate

Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices

Layer formation with reduced channel loss

Method of making a semiconductor device using sacrificial fins

Memory device having multiple dielectric gate stacks and related methods

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Facet-free strained silicon transistor

Facet-free strained silicon transistor

Fully substrate-isolated FinFET transistor

Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Transistor having a stressed body

Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods

IBM

Dual shallow trench isolation liner for preventing electrical shorts

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

Dual shallow trench isolation liner for preventing electrical shorts

Dual shallow trench isolation liner for preventing electrical shorts

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

LIU QING

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Semiconductor device with an inclined source/drain and associated methods

Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods

Isolation regions for SOI devices

BELL SEMICONDUCTOR LLC

Method of making a semiconductor device using a dummy gate

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

Method to co-integrate SiGe and Si channels for finFET devices

Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods

GLOBALFOUNDRIES INC

Fin transformation process and isolation structures facilitating different Fin isolation schemes

Process for faciltiating fin isolation schemes

Fin isolation structures facilitating different fin isolation schemes

LOUBET NICOLAS

Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering

Layer formation with reduced channel loss

KHARE PRASANNA

Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication

Method and apparatus for buried-channel semiconductor device

DORIS BRUCE B

Dual shallow trench isolation liner for preventing electrical shorts