Inventor

LAPLANCHE YVES THOMAS

FR9 patents

⚠️ This page may combine multiple inventors who share the name “LAPLANCHE YVES THOMAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADVANCED RISC MACH LTD

5 patents

US10355674B2Jul 16, 2019

HOLD BETINA

1 patent

US9105315B2Aug 11, 2015

Controlling the voltage level on the word line to maintain performance and reduce access disturbs

HOLD BETINA12 citations78

LAPLANCHE YVES THOMAS

1 patent

US8779787B2Jul 15, 2014

Apparatus and method for determining variation in a predetermined physical property of a circuit

LAPLANCHE YVES THOMAS6 citations65

PELLOIE JEAN-LUC

1 patent

US8219950B2Jul 10, 2012

Propagation delay time balancing in chained inverting devices

PELLOIE JEAN-LUC2 citations57

PELLOIE JEAN LUC

1 patent

US8924766B2Dec 30, 2014

Analysing timing paths for circuits formed of standard cells

PELLOIE JEAN LUC1 citations46

LAPLANCHE YVES THOMAS

ADVANCED RISC MACH LTD

Clock gating circuit

Multi-bit scan chain with error-bit generator

Current measurement architecture

Via coloring methods and systems

Cell bridging technique

HOLD BETINA

Controlling the voltage level on the word line to maintain performance and reduce access disturbs

LAPLANCHE YVES THOMAS

Apparatus and method for determining variation in a predetermined physical property of a circuit

PELLOIE JEAN-LUC

Propagation delay time balancing in chained inverting devices

PELLOIE JEAN LUC

Analysing timing paths for circuits formed of standard cells