Inventor

JOU CHEWN-PU

TW305 patents

⚠️ This page may combine multiple inventors who share the name “JOU CHEWN-PU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOU CHEWN-PU

TAIWAN SEMICONDUCTOR MFG CO LTD

Antenna cavity structure for integrated patch antenna in integrated fan-out packaging

Vertical metal insulator metal capacitor

Antenna cavity structure for integrated patch antenna in integrated fan-out packaging

Integrated fan-out package with 3D magnetic core inductor

Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator

Fiber-to-chip grating coupler for photonic circuits

Optical device and method of manufacturing the same

Optical modulator and package

3D IC decoupling capacitor structure and method for manufacturing the same

Chip package having integrated capacitor

Semiconductor device and method

Varainductor, voltage controlled oscillator including the varainductor, and phase locked loop including the varainductor

High resolution time-to-digital convertor

Transmission line design and method, where high-k dielectric surrounds the transmission line for increased isolation

Radio frequency interconnect

Phase locked loop including a varainductor

Phase-locked loop circuit

FinFET varactor

Ultra-low voltage-controlled oscillator with trifilar coupling

Integrated circuit stack verification method and system for performing the same

Integrated circuit stack verification method and system for performing the same

Method of fabricating semiconductor structure with heating element

TAIWAN SEMICONDUCTOR MFG

PVT-free calibration circuit for TDC resolution in ADPLL

Gate controlled bipolar junction transistor on fin-like field effect transistor (FinFET) structure

Method and apparatus of voltage scaling techniques

Multi-gate and complementary varactors in FinFET process

RF switch on high resistive substrate

Phase-locked loop circuit

Phase-locked loop (PLL)

Reference voltage generators, integrated circuits, and methods for operating the reference voltage generators

JOU CHEWN-PU

Reducing high-frequency signal loss in substrates

Methods and apparatus for reduced gate resistance finFET

Vertical metal insulator metal capacitor

HSIEH HSIEH-HUNG

Low-noise amplifier with gain enhancement

CMOS millimeter-wave variable-gain low-noise amplifier

Amplifier with floating well

KUO FENG WEI

Phase-locked loops that share a loop filter

Lock detector and method of detecting lock status for phase lock loop

Bead for 2.5D/3D chip packaging application

CHEN YEN-JEN

Divider-less phase locked loop (PLL)

Auto frequency calibration for a phase locked loop and method of use

CHEN CHIA-CHUNG

Noise decoupling structure with through-substrate vias

Gated-varactors

TSAI MING-HSIEN

Junction varactor for ESD protection of RF circuits

ESD protection circuit for RFID tag

LIN YU-LING

Slot-shielded coplanar strip-line compatible with CMOS processes

Integrated circuit ground shielding structure

CHEN HUAN-NENG

Up-conversion mixer having a reduced third order harmonic

WANG MILL-JER

Three-dimensional integrated circuit and method for wireless information access thereof

WANG YOU-JEN

Method and system for time to digital conversion with calibration and correction loops