Inventor

SINGH RAVI P

US45 patents

⚠️ This page may combine multiple inventors who share the name “SINGH RAVI P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINGH RAVI P

ANALOG DEVICES INC

Processor stalling

Single-step processing and selecting debugging modes

FIFO write/LIFO read trace buffer with software and hardware loop compression

Hardware loops

Data synchronization for a test access port

Early exception detection

Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination

Early exception detection

Decode and dispatch of multi-issue and multiple width instructions

Hardware loops and pipeline system using advanced generation of loop parameters

Self-nesting interrupts

Efficient emulation instruction dispatch based on instruction width

Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism

Multi-cycle instructions

Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor

Valid bit generation and tracking in a pipelined processor

Variable width alignment engine for aligning instructions based on transition between buffers

NVIDIA CORP

Built-in self-test for a programmable vision accelerator of a system on a chip

Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip

Performing multiple point table lookups in a single cycle in a system on chip

Hardware accelerated anomaly detection using a min/max collector in a system on a chip

Using a hardware sequencer in a direct memory access system of a system on a chip

Programmable vision accelerator

Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip

Using a hardware sequencer in a direct memory access system of a system on a chip

Using per memory bank load caches for reducing power use in a system on a chip

Built-in self-test for a programmable vision accelerator of a system on a chip

Hardware accelerated anomaly detection using a min/max collector in a system on a chip

Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip

Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip

Using per memory bank load caches for reducing power use in a system on a chip

Performing load and permute with a single instruction in a system on a chip

Performing load and store operations of 2D arrays in a single cycle in a system on a chip

Reduced memory write requirements in a system on a chip using automatic store predication

INTEL CORP

Exception handling using an exception pipeline in a pipelined processor

Valid bit generation and tracking in a pipelined processor

Hardware loops

Resetting a programmable processor

Event handling

Hardware loops

Watchpoint engine for a pipelined processor

Instruction address generation and tracking in a pipelined processor

Register move operations

Processor reset and instruction fetches

Security on hardware loops