Inventor

TSAO PEI-HAW

TW91 patents

⚠️ This page may combine multiple inventors who share the name “TSAO PEI-HAW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAO PEI-HAW

TAIWAN SEMICONDUCTOR MFG

Enhanced copper posts for wafer level chip scale packaging

Wire stitch bond on an integrated circuit bond pad and method of making the same

Under bump metallization structure

Electrical performance enhanced wafer level chip scale package with ground

Method of wafer level chip scale packaging

System-in-package packaging for minimizing bond wire contamination and yield loss

Method for fabricating an under bump metallization structure

Microelectronic assembly with stiffening member

Metal patterned structure for SiN surface adhesion enhancement

Enhanced copper posts for wafer level chip scale packaging

Bonding and probing pad structures

Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

Method to increase bump height and achieve robust bump structure

Method of protecting a passivation layer during solder bump formation

Substrate design to improve chip package reliability

Method of fabricating as grooved heat spreader for stress reduction in an IC package

Implementation of protection layer for bond pad protection

Semiconductor bond pad structures and methods of manufacturing thereof

Method and apparatus for increasing heat dissipation of high performance integrated circuits (IC)

Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly

Structure and method for low-stress concentration solder bumps

Buildup substrate pad pre-solder bump manufacturing

Bump pattern design for flip chip semiconductor package

Heat spreader and package structure utilizing the same

Protected solder ball joints in wafer level chip-scale packaging

Flip chip packages with spacers separating heat sinks and substrates

Method for protecting the front side of semiconductor wafers

TAIWAN SEMICONDUCTOR MFG CO LTD

Package structure with protrusion structure

Magnetic shielding material with insulator-coated ferromagnetic particles

Package and printed circuit board attachment

Wafer structure and packaging method

Edge crack detection system

Seal rings structures in semiconductor device interconnect layers and methods of forming the same

Magnetic shielding material with insulator-coated ferromagnetic particles

Package and printed circuit board attachment

Carrier tape system and methods of using carrier tape system

Printed circuit board

Semiconductor structure and manufacturing method thereof

Package structure and method for forming the same

Semiconductor structure having a conductive bump with a plurality of bump segments

Edge crack detection system

Carrier tape system and methods of making and using the same

Method of forming integrated circuit packages by bonding package component having first carrier to package substrate having second carrier

Chip structure

VANGUARD INT SEMICONDUCT CORP

Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength

Magnetic insert into mold cavity to prevent resin bleeding from bond area of pre-mold (open cavity) plastic chip carrier during molding process

TAIWAN SEMINCONDUCTOR MFG CO L

Solder bump structure and method of manufacturing same

WANG CHUNG YU

Protected solder ball joints in wafer level chip-scale packaging

LIU YU-WEN

Underbump metallization structure