Inventor
LIVNE SARIG
IL15 patents
⚠️ This page may combine multiple inventors who share the name “LIVNE SARIG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
6 patentsUS12212504B2Jan 28, 2025
Techniques to use descriptors for packet transmit scheduling
INTEL CORP0 citations61
US10951475B2Mar 16, 2021
Technologies for transmit scheduler dynamic configurations
INTEL CORP0 citations61
US10812402B2Oct 20, 2020
Shaping of post-scheduling network pipeline jitter
INTEL CORP1 citations58
US12381824B2Aug 5, 2025
Load balancing among output ports
INTEL CORP0 citations55
US10791057B2Sep 29, 2020
Techniques for packet transmit scheduling
INTEL CORP0 citations47
US12388760B2Aug 12, 2025
Packet transmission scheduling fairness
INTEL CORP0 citations43
SUKONIK VITALY
4 patentsUS8615629B2Dec 24, 2013
Access scheduler
SUKONIK VITALY4 citations57
US8838853B2Sep 16, 2014
Access buffer
SUKONIK VITALY1 citations49
US9769092B2Sep 19, 2017
Packet buffer comprising a data section and a data description section
SUKONIK VITALY0 citations47
US9749255B2Aug 29, 2017
Method, network device, computer program and computer program product for communication queue state
SUKONIK VITALY1 citations47
CISCO TECH INC
3 patentsUS7606250B2Oct 20, 2009
Assigning resources to items such as processing contexts for processing packets
CISCO TECH INC7 citations72
US7561589B2Jul 14, 2009
Virtual address storage which may be of particular use in generating fragmented packets
CISCO TECH INC2 citations61
US7075940B1Jul 11, 2006
Method and apparatus for generating and using dynamic mappings between sets of entities such as between output queues and ports in a communications system
CISCO TECH INC1 citations46