Inventor
ALEXANDER GREGORY WILLIAM
US31 patents
Patents
31 patentsUS7120784B2Oct 10, 2006
Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment
IBM23 citations92
US7254678B2Aug 7, 2007
Enhanced STCX design to improve subsequent load efficiency
IBM38 citations89
US11487672B1Nov 1, 2022
Multiple copy scoping bits for cache memory
IBM7 citations82
US7039768B2May 2, 2006
Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions
IBM10 citations74
US10929142B2Feb 23, 2021
Making precise operand-store-compare predictions to avoid false dependencies
IBM3 citations70
US11907125B2Feb 20, 2024
Hot line fairness mechanism favoring software forward progress
IBM0 citations61
US11748266B1Sep 5, 2023
Special tracking pool enhancement for core local cache address invalidates
IBM0 citations61
US11182168B2Nov 23, 2021
Post completion execution in an out-of-order processor design
IBM0 citations61
US11068303B2Jul 20, 2021
Adjusting thread balancing in response to disruptive complex instruction
IBM1 citations61
US10956168B2Mar 23, 2021
Post completion execution in an out-of-order processor design
IBM1 citations61
US12493553B2Dec 9, 2025
Cross-core invalidation snapshot management
IBM0 citations60
US12038841B2Jul 16, 2024
Decentralized hot cache line tracking fairness mechanism
IBM1 citations60
US11977486B2May 7, 2024
Shadow pointer directory in an inclusive hierarchical cache
IBM0 citations60
US11853212B2Dec 26, 2023
Preemptive tracking of remote requests for decentralized hot cache line fairness tracking
IBM1 citations60
US11782836B1Oct 10, 2023
Multiprocessor system cache management with non-authority designation
IBM0 citations60
US12585593B2Mar 24, 2026
Processor cross-core cache line contention management
IBM0 citations59
US12099845B2Sep 24, 2024
Load reissuing using an alternate issue queue
IBM0 citations59
US11989128B1May 21, 2024
Invalidity protection for shared cache lines
IBM0 citations59
US11907132B2Feb 20, 2024
Final cache directory state indication
IBM0 citations59
US11782777B1Oct 10, 2023
Preventing extraneous messages when exiting core recovery
IBM0 citations59
US11256511B2Feb 22, 2022
Instruction scheduling during execution in a processor
IBM0 citations51
US12423234B1Sep 23, 2025
Cache governance in a computing environment with multiple processors
IBM0 citations50
US11620231B2Apr 4, 2023
Lateral persistence directory states
IBM0 citations50
US11144321B2Oct 12, 2021
Store hit multiple load side register for preventing a subsequent store memory violation
IBM0 citations50
US11113055B2Sep 7, 2021
Store instruction to store instruction dependency
IBM0 citations50
US11880304B2Jan 23, 2024
Cache management using cache scope designation
IBM0 citations49
US10977041B2Apr 13, 2021
Offset-based mechanism for storage in global completion tables
IBM0 citations48
US10963259B2Mar 30, 2021
Accounting for multiple pipeline depths in processor instrumentation
IBM0 citations47
US11144367B2Oct 12, 2021
Write power optimization for hardware employing pipe-based duplicate register files
IBM0 citations46
US11205005B2Dec 21, 2021
Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data
IBM0 citations44
US10802830B2Oct 13, 2020
Imprecise register dependency tracking
IBM0 citations33