Inventor

SCHEUNEMAN JAMES H

22 patents

⚠️ This page may combine multiple inventors who share the name “SCHEUNEMAN JAMES H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHEUNEMAN JAMES H

UNISYS CORP

Memory access system for pipelined data paths to and from storage

Pipelined data stack with access through-checking

Fault capture/fault injection system

Error correction check during write cycles

Unconditional clock and automatic refresh logic

Partial duplication of pipelined stack with data integrity checking

Bus data transmission verification system

Bank initiate error detection

System for addressing a multibank memory system

Accessing control with predetermined priority based on a feedback arrangement

Pipelined address check bit stack controller

Failure detection for partial write operations for memories

SPERRY CORP

High performance storage unit

Pipelined split stack with high performance interleaved decode

Memory through checking system with comparison of data word parity before and after ECC processing

Multiple output port memory storage module

Multiple port memory with port decode error detector

Hidden memory refresh

One word buffer memory system

Multiple unit adapter

SPERRY RAND CORP

Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory

Double bit error correction using double bit complementing