Inventor
GANUSOV ILYA K
US22 patents
⚠️ This page may combine multiple inventors who share the name “GANUSOV ILYA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
17 patentsUS10069486B1Sep 4, 2018
Multimode registers with pulse latches
XILINX INC7 citations83
US10049177B1Aug 14, 2018
Circuits for and methods of reducing power consumed by routing clock signals in an integrated
XILINX INC9 citations83
US9875330B2Jan 23, 2018
Folding duplicate instances of modules in a circuit design
XILINX INC7 citations83
US9577615B1Feb 21, 2017
Circuits for and methods of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking
XILINX INC8 citations83
US9531351B1Dec 27, 2016
Configurable latch circuit
XILINX INC8 citations83
US8988125B1Mar 24, 2015
Circuits for and methods of routing signals in an integrated circuit
XILINX INC8 citations83
US10284185B1May 7, 2019
Selectively providing clock signals using a programmable control circuit
XILINX INC10 citations82
US9842187B1Dec 12, 2017
Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design
XILINX INC9 citations82
US10340898B1Jul 2, 2019
Configurable latch circuit
XILINX INC2 citations72
US10320386B1Jun 11, 2019
Programmable pipeline interface circuit
XILINX INC4 citations72
US9729153B1Aug 8, 2017
Multimode multiplexer-based circuit
XILINX INC3 citations72
US9537491B1Jan 3, 2017
Leaf-level generation of phase-shifted clocks using programmable clock delays
XILINX INC6 citations72
US9118310B1Aug 25, 2015
Programmable delay circuit block
XILINX INC6 citations72
US9836568B1Dec 5, 2017
Programmable integrated circuit design flow using timing-driven pipeline analysis
XILINX INC6 citations69
US10230374B1Mar 12, 2019
Methods and circuits for preventing hold violations
XILINX INC1 citations62
US9372953B1Jun 21, 2016
Increasing operating frequency of circuit designs using dynamically modified timing constraints
XILINX INC2 citations55
US9954534B2Apr 24, 2018
Methods and circuits for preventing hold time violations
XILINX INC0 citations40
INTEL CORP
5 patentsUS12164462B2Dec 10, 2024
Micro-network-on-chip and microsector infrastructure
INTEL CORP2 citations72
US12248021B2Mar 11, 2025
Debug trace microsectors
INTEL CORP1 citations64
US11960734B2Apr 16, 2024
Logic fabric based on microsector infrastructure with data register having scan registers
INTEL CORP0 citations62
US11901896B2Feb 13, 2024
Soft network-on-chip overlay through a partial reconfiguration region
INTEL CORP0 citations59
US12197360B2Jan 14, 2025
At-speed burst sampling for user registers
INTEL CORP0 citations58