Inventor
GARINGER NED D
US12 patents
⚠️ This page may combine multiple inventors who share the name “GARINGER NED D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VLSI TECHNOLOGY INC
7 patentsUS5892978AApr 6, 1999
Combined consective byte update buffer
VLSI TECHNOLOGY INC36 citations91
US5336940AAug 9, 1994
Delay-compensated output pad for an integrated circuit and method therefor
VLSI TECHNOLOGY INC34 citations91
US5252867AOct 12, 1993
Self-compensating digital delay semiconductor device with selectable output delays and method therefor
VLSI TECHNOLOGY INC50 citations91
US5136180AAug 4, 1992
Variable frequency clock for a computer system
VLSI TECHNOLOGY INC41 citations89
US6145047ANov 7, 2000
Circuit and method for converting interrupt signals from level trigger mode to edge trigger mode
VLSI TECHNOLOGY INC13 citations72
US5365130ANov 15, 1994
Self-compensating output pad for an integrated circuit and method therefor
VLSI TECHNOLOGY INC17 citations72
US5281874AJan 25, 1994
Compensated digital delay semiconductor device with selectable output taps and method therefor
VLSI TECHNOLOGY INC11 citations72
FREESCALE SEMICONDUCTOR INC
5 patentsUS7277449B2Oct 2, 2007
On chip network
FREESCALE SEMICONDUCTOR INC21 citations91
US7200137B2Apr 3, 2007
On chip network that maximizes interconnect utilization between processing elements
FREESCALE SEMICONDUCTOR INC30 citations91
US7051150B2May 23, 2006
Scalable on chip network
FREESCALE SEMICONDUCTOR INC41 citations91
US6996651B2Feb 7, 2006
On chip network with memory device address decoding
FREESCALE SEMICONDUCTOR INC31 citations91
US7139860B2Nov 21, 2006
On chip network with independent logical and physical layers
FREESCALE SEMICONDUCTOR INC13 citations82