Inventor

HAGERSTEN ERIK

US32 patents

⚠️ This page may combine multiple inventors who share the name “HAGERSTEN ERIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAGERSTEN ERIK

SUN MICROSYSTEMS INC

Directory-based, shared-memory, scaleable multiprocessor computer system having deadlock-free transaction flow sans flow control protocol

System and method for accessing a shared computer resource using a lock featuring different spin speeds corresponding to multiple states

Method and apparatus providing short latency round-robin arbitration for access to a shared resource

Implementing snooping on a split-transaction computer system bus

Hybrid NUMA COMA caching system and methods for selecting between the caching modes

Split transaction snooping bus protocol

Hybrid NUMA COMA caching system and methods for selecting between the caching modes

Hybrid NUMA COMA caching system and methods for selecting between the caching modes

Hybrid queue and backoff computer resource lock featuring different spin speeds corresponding to multiple-states

Method for increasing the speed of data processing in a computer system

Deterministic distributed multi-cache coherence method and system

Optimizing responses in a coherent distributed electronic system including a computer system

Method and system for predicting addresses and prefetching data into a cache memory

Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure

Method and apparatus extending coherence domain beyond a computer system bus

Interrupt transfer management process and system for a multi-processor environment

Queuing delay limiter

Multiprocessing systems employing hierarchical back-off locks

SAMSUNG ELECTRONICS CO LTD

Placement policy for memory hierarchies

Efficient early ordering mechanism

Systems and methods for direct data access in multi-level cache memory hierarchies

Systems and methods for implementing coherent memory in a multiprocessor system

Efficient early ordering mechanism

Systems and methods for implementing coherent memory in a multiprocessor system

Systems and methods for implementing coherent memory in a multiprocessor system

Systems and methods for reducing first level cache energy by eliminating cache address tags

Systems and methods for implementing a tag-less shared cache and a larger backing cache

Tracking alternative cacheline placement locations in a cache hierarchy

Management of shared pipeline resource usage based on level information

BERG ERIK

System for and method of capturing performance characteristics data from a computer system and modeling target system performance

System for and method of capturing application characteristics data from a computer system and modeling target system

System for and method of capturing application characteristics data from a computer system and modeling target system