Inventor

ANG TING CHEONG

SG49 patents

⚠️ This page may combine multiple inventors who share the name “ANG TING CHEONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANG TING CHEONG

CHARTERED SEMICONDUCTOR MFG

Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection

Method to form, and structure of, a dual damascene interconnect device

Method for fabricating an air gap shallow trench isolation (STI) structure

Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures

Method of forming PID protection diode for SOI wafer

Method for fabricating a MOS device

High-K MOM capacitor

Method of body contact for SOI mosfet

Method of hard mask patterning

Method of forming PID protection diode for SOI wafer

Low voltage controllable transient trigger network for ESD protection

ESD protection device for STI deep submicron technology

Copper metal structure for the reduction of intra-metal capacitance

Process to fabricate a novel source-drain extension

Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions

Method of fabrication of dual gate oxides for CMOS devices

Method for forming a raised source and drain without using selective epitaxial growth

Triple-layered low dielectric constant dielectric dual damascene approach

Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate

Method of field isolation in silicon-on-insulator technology

Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions

Method of body contact for SOI MOSFET

Copper metal structure for the reduction of intra-metal capacitance

Simplified method of fabricating a rim phase shift mask

Vertical source/drain contact semiconductor

Alternating phase shift mask and method for fabricating the alignment monitor

Process to fabricate a source-drain extension

Vertical source/drain contact semiconductor

Method of forming a high K metallic dielectric layer

Method of forming of high K metallic dielectric layer

ESD protection network used for SOI technology

Method of vacuum packaging a semiconductor device assembly

Thick oxide MOS device used in ESD protection circuit

Method of fabrication of low leakage capacitor

Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers

ESD protection device for SOI technology

Double-layered low dielectric constant dielectric dual damascene method

Method of vacuum packaging a semiconductor device assembly

SEMICONDUCTOR MFG INT SHANGHAI

Method with high gapfill capability for semiconductor devices

Method with high gapfill capability for semiconductor devices

Method of improving a shallow trench isolation gapfill process

Method for forming low dielectric constant fluorine-doped layers

Method for forming low dielectric constant fluorine-doped layers

ANG TING CHEONG

Method of eliminating micro-trenches during spacer etch

Semiconductor trench structure having a silicon nitride layer overlaying an oxide layer

Method and system for metal barrier and seed integration

Method of improving adhesion strength of low dielectric constant layers

CHARTERED SEMINCONDUCTOR MFG L

Method of fabricating wedge isolation transistors

DENSELIGHT SEMICONDUCTOR PTE L

Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor