Inventor

GRUENING ULRIKE

DE63 patents

⚠️ This page may combine multiple inventors who share the name “GRUENING ULRIKE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRUENING ULRIKE

IBM

Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch

Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect

Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch

Embedded vertical DRAM cells and dual workfunction logic gates

Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

Low-resistance salicide fill for trench capacitors

Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect

Semiconductor memory device with reduced orientation-dependent oxidation in trench structures

Process for manufacturing a crystal axis-aligned vertical side wall device

Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure

Crystal-axis-aligned vertical side wall device

Capacitor trench-top dielectric for self-aligned device isolation

Vertical DRAM cell with wordline self-aligned to storage trench

Process for fabricating a uniform gate oxide of a vertical transistor

Collar process for reduced deep trench edge bias

Process for buried-strap self-aligned to deep storage trench

Self-aligned near surface strap for high density trench DRAMS

INFINEON TECHNOLOGIES AG

Compact trench capacitor memory cell with body contact

Dynamic random access memory

Trench capacitor memory cell

Memory cell for plateline sensing

Use of dummy poly spacers and divot fill techniques for DT-aligned processing after STI formation for advanced deep trench capacitor DRAM

Semiconductor structures and manufacturing methods

Structure and method for forming a body contact for vertical transistor cells

Self-aligned buried strap for vertical transistors

Locally folded split level bitline wiring

Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates

Integrated circuit trench device with a dielectric collar stack, and method of forming thereof

Dynamic random access memory

Optical structure and method for producing the same

Method of producing an open form

Control of oxide thickness in vertical transistor structures

Apparatus and method for forming controlled deep trench top isolation layers

Reducing impact of coupling noise in multi-level bitline architecture

INFINEON TECHNOLOGIES CORP

Formation of controlled trench top isolation layers for vertical transistors

Single sided buried strap

Semiconductor structure and manufacturing methods

Reducing impact of coupling noise

Field-shield-trench isolation for gigabit DRAMs

Process for manufacture of trench DRAM capacitor buried plates

Dynamic random access memory

Formation of controlled trench top isolation layers for vertical transistors

SIEMENS AG

Memory cell structure and fabrication

Apparatus and method for forming controlled deep trench top isolation layers

Optical structure and method for its production

Method of operating a storage cell arrangement

Buffer layer for improving control of layer thickness

Method for fabricating transistors

Memory cell structure and fabrication